參數(shù)資料
型號(hào)： 9UMS9610CKLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48
封裝： 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 134K
代理商： 9UMS9610CKLF
IDTTM/ICSTM PC MAIN CLOCK
1336—06/01/09
ICS9UMS9610
PC MAIN CLOCK
11
Byte
2
Output Enable Register
Bit(s)
Pin #
Name
Description
Type
0
1
Default
7
CPU0 Enable
This bit controls whether the CPU[0] output
buffer is enabled or not.
RW
0 = Disabled
1 = Enabled
1
6
CPU1 Enable
This bit controls whether the CPU[1] output
buffer is enabled or not.
RW
0 = Disabled
1 = Enabled
1
5
CPU2 Enable
This bit controls whether the CPU[2] output
buffer is enabled or not.
RW
0 = Disabled
1 = Enabled
1
4
SRC0 Enable
This bit controls whether the SRC[0] output
buffer is enabled or not.
RW
0 = Disabled
1 = Enabled
1
3
SRC1 Enable
This bit controls whether the SRC[1] output
buffer is enabled or not.
RW
0 = Disabled
1 = Enabled
1
2
SRC2 Enable
This bit controls whether the SRC[2] output
buffer is enabled or not.
RW
0 = Disabled
1 = Enabled
1
DOT Enable
This bit controls whether the DOT output
buffer is enabled or not.
RW
0 = Disabled
1 = Enabled
1
0
LCD100 Enable
This bit controls whether the LCD output buffer
is enabled or not.
RW
0 = Disabled
1 = Enabled
1
Byte
3
Output Control Register
Bit(s)
Pin #
Name
Description
Type
0
1
Default
7
Reserved
0
6
Reserved
0
5
REF Enable
This bit controls whether the REF output
buffer is enabled or not.
RW
0 = Disabled
1 = Enabled
1
4
3
2
CPU0 Stop
Enable
This bit controls whether the CPU[0] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[0] output buffer will be
disabled with the assertion of CPU_STP#.
RW
Free Running
Stoppable
0
1
CPU1 Stop
Enable
This bit controls whether the CPU[1] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[1] output buffer will be
disabled with the assertion of CPU_STP#.
RW
Free Running
Stoppable
0
CPU2 Stop
Enable
This bit controls whether the CPU[2] output
buffer is free-running or stoppable. If it is set
to stoppable the CPU[2] output buffer will be
disabled with the assertion of CPU_STP#.
RW
Free Running
Stoppable
0
10
00 = Slow Edge Rate
01 = Medium Edge Rate
10 = Fast Edge Rate
11 = Reserved
RW
These bits control the edge rate of the REF
clock.
REF Slew
相關(guān)PDF資料
PDF描述
9UMS9633BFILFT 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9UMS9633BKILFT 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48
9UMS9633BFLFT OTHER CLOCK GENERATOR, PDSO48
9ZX21501CKLFT 9ZX SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64
9ZX21501CKLF 9ZX SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9UMS9610CKLFT 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
9UMS9633 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE
9UMS9633BFILF 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
9UMS9633BFILFT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
9UMS9633BFW3LFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE
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