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參數(shù)資料
| 型號： | 9UMS9610CKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 134K |
| 代理商： | 9UMS9610CKLF |
IDTTM/ICSTM PC MAIN CLOCK
1336—06/01/09
ICS9UMS9610
PC MAIN CLOCK
10
Byte
0
PLL & Divider Enable Register
Bit(s)
Pin #
Name
Description
Type
0
1
Default
7
-
PLL1 Enable
This bit controls whether the PLL driving the
CPU and SRC clocks is enabled or not.
RW
0 = Disabled
1 = Enabled
1
6
-
PLL2 Enable
This bit controls whether the PLL driving the
DOT and clock is enabled or not.
RW
0 = Disabled
1 = Enabled
1
5
-
PLL3 Enable
This bit controls whether the PLL driving the
LCD clock is enabled or not.
RW
0 = Disabled
1 = Enabled
1
4-
0
3-
CPU Divider
Enable
This bit controls whether the CPU output
divider is enabled or not.
NOTE: This bit should be automatically set to
‘0’ if bit 7 is set to ‘0’.
RW
0 = Disabled
1 = Enabled
1
2-
SRC Output
Divider Enable
This bit controls whether the SRC output
divider is enabled or not.
NOTE: This bit should be automatically set to
‘0’ if bit 7 is set to ‘0’.
RW
0 = Disabled
1 = Enabled
1
1-
LCD Output
Divider Enable
This bit controls whether the LCD output
divider is enabled or not.
NOTE: This bit should be automatically set to
‘0’ if bit 5 is set to ‘0’.
RW
0 = Disabled
1 = Enabled
1
0-
DOT Output
Divider Enable
This bit controls whether the DOT output
divider is enabled or not.
NOTE: This bit should be automatically set to
‘0’ if bit 6 is set to ‘0’.
RW
0 = Disabled
1 = Enabled
1
Byte
1
PLL SS Enable/Control Register
Bit(s)
Pin #
Name
Description
Type
0
1
Default
7
PLL1 SS Enable
This bit controls whether PLL1 has spread
enabled or not. Spread spectrum for PLL1 is
set at -0.5% down-spread. Note that PLL1
drives the CPU and SRC clocks.
RW
0 = Disabled
1 = Enabled
1
6
PLL3 SS Enable
This bit controls whether PLL3 has spread
enabled or not. Note that PLL3 drives the SSC
clock, and that the spread spectrum amount is
set in bits 3-5.
RW
0 = Disabled
1 = Enabled
1
5
0
4
0
3
0
2
Reserved
0
1
Reserved
0
Reserved
0
Reserved
See Table 2: LCD Spread Select
Table
PLL3 FS Select
These 3 bits select the frequency of PLL3 and
the SSC clock when Byte 1 Bit 6 (PLL3
Spread Spectrum Enable) is set.
RW
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PDF描述 |
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| 9UMS9633BFILFT | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9UMS9633BKILFT | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 9UMS9633BFLFT | OTHER CLOCK GENERATOR, PDSO48 |
| 9ZX21501CKLFT | 9ZX SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64 |
| 9ZX21501CKLF | 9ZX SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9UMS9610CKLFT | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| 9UMS9633 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE |
| 9UMS9633BFILF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9UMS9633BFILFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9UMS9633BFW3LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE |
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