參數資料
型號: 9LPRS502YKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQCC56
封裝: ROHS COMPLIANT, MLF-56
文件頁數: 25/29頁
文件大?。?/td> 272K
代理商: 9LPRS502YKLFT
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125A—02/19/08
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
5
Datasheet
SSOP/TSSOP Pin Description (Continued)
Fully Integrated Regulator Connection for Desktop/Mobile Applications
PIN #
PIN NAME
TYPE
DESCRIPTION
48
CK_PWRGD/PD#
IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
49
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS
and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider
mode while in test mode. Refer to Test Clarification Table.
50
GNDREF
PWR
Ground pin for crystal oscillator circuit
51
X2
OUT
Crystal output, nominally 14.318MHz.
52
X1
IN
Crystal input, Nominally 14.318MHz.
53
VDDREF
PWR
Power pin for the REF outputs, 3.3V nominal.
54
REF0/FSLC/TEST_SEL
I/O
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched
input to enable test mode. Refer to Test Clarification Table.
55
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
56
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
1.05V to 3.3V
(+/-5%)
NC
PIN 40
CPU_IO Decoupling
Network
96_IO Decoupling
Network
ICS9LPR502
ICS9LPRS502
VDDCPU_IO, Pin 41
VDDSRC_IO Pin 37, 26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
PLL3_IO Decoupling
Network
SRC_IO Decoupling
Network
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