
6
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
1391D—02/02/09
TSSOP Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
33
VDDATIG
PWR
Power supply for ATIG core, nominal 3.3V
34
ATIG1C_LPRS
OUT
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)
35
ATIG1T_LPRS
OUT
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed)
36
ATIG0C_LPRS
OUT
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)
37
ATIG0T_LPRS
OUT
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed)
38
SB_SRC1C_LPRS
OUT
Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor
to GND and no 33 ohm series resistor needed
39
SB_SRC1T_LPRS
OUT
True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
40
GNDSB_SRC
GND
Ground pin for the SB_SRC outputs
41
VDDSB_SRC_IO
PWR
Power supply for differential SB_SRC outputs, nominal 1.05V to 3.3V
42
VDDSB_SRC
PWR
Supply for SB SRC PLL core, 3.3V nominal
43
SB_SRC0C_LPRS
OUT
Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor
to GND and no 33 ohm series resistor needed
44
SB_SRC0T_LPRS
OUT
True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
45
CLKREQ4#*
IN
Clock Request pin for SRC4 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
46
CLKREQ3#*
IN
Clock Request pin for SRC3 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
47
VDDSATA
PWR
Power supply for SATA core logic, nominal 3.3V
48
SRC6C/SATAC_LPRS
OUT
Complement clock of low power differential SRC/SATA clock pair. (no 50ohm shunt resistor to GND and
no 33 ohm series resistor needed)
49
SRC6T/SATAT_LPRS
OUT
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed)
50
GNDSATA
GND
Ground pin for the SRC outputs
51
CLKREQ2#*
IN
Clock Request pin for SRC2 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
52
CLKREQ1#*
IN
Clock Request pin for SRC1 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
53
GNDCPU
GND
Ground pin for the CPU outputs
54
VDDCPU_IO
PWR
Power supply for differential CPU outputs, nominal 1.05V to 3.3V
55
VDDCPU
PWR
Supply for CPU core, 3.3V nominal
56
CPUKG0C_LPRS
OUT
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated
series resistor. (no 33 ohm series resistor needed)
57
CPUKG0T_LPRS
OUT
True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series
resistor.(no 33 ohm series resistor needed)
58
PD#
IN
Enter /Exit Power Down.
0 = Power Down, 1 = normal operation.
59
GNDHTT
PWR
Ground pin for the HTT outputs
60
HTT0C_LPRS/66M
OUT
Complementary signal of low-power differential push-pull hypertransport clock with integrated series
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 1.8V single ended
66MHz hyper transport clock
61
HTT0T_LPRS/66M
OUT
True signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed) /1.8V single ended 66MHz hyper
transport clock
62
VDDHTT
PWR
Supply for HTT clocks, nominal 3.3V.
63
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
64
REF2/SEL_27
I/O
14.318 MHz reference clock, 3.3V/3.3V Latched input to select 27MHz SS and non SS on SRC7
0 = 100MHz differential spreading SRC clock, 1 = 27MHz non-spreading singled clock on pin 12 and
27MHz spread clock on pin 13.