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參數(shù)資料
| 型號： | 9LP525BF-2LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大小： | 226K |
| 代理商： | 9LP525BF-2LFT |
IDTTM/ICSTM PC MAIN CLOCK
1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
3
Pin Description (continued)
PIN #
PIN N A ME
TYPE
D ESC R IPTION
25
SRCC3/CR#_D
I/O
Complementary c loc k of differential SRC c loc k pair/ Cloc k Reques t c ontrol D for either SRC1 or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may als o be us ed as a Cloc k Reques t c ontrol of SRC pair 1 or SRC pair 4
v ia SMBus . Before c onfiguring this pin as a Cloc k Reques t Pin, the SRC output mus t firs t be dis abled in by te 4, bit 7 of SMBus
addres s s pac e . After the SRC output is dis abled, the pin c an then be s et to s erv e as a Cloc k Reques t pin for either SRC pair 1 or
pair 4 us ing the CRD#_EN bit loc ated in by te 5 of SMBUs addres s s pac e.
By te 5, bit 1
0 = SRC3 enabled (default)
1= CRD# enabled. By te 5, bit 0 c ontrols whether CRD# c ontrols SRC1 or SRC4 pair
By te 5, bit 0
0 = CRD# c ontrols SRC1 pair (default),
1= CRD# c ontrols SRC4 pair
26
VDDSRC_IO
PWR
Power s upply for SRC c loc k s . 0.8V nominal from s ourc e/emitter of ex ternal pas s trans is tor
27
SRCT4
O UT
True c loc k of low power differential SRC c loc k pair.
28
SRCC4
O UT
Complement c loc k of low power differential SRC c loc k pair.
29
CPU_ST O P#/SRCC5
I/O
Ref, XTAL power s upply , nominal 3.3V
30
PCI_ST O P#/SRCT 5
I/O
Stops all PCICLKs at logic 0 lev el, when low. F ree running PCICLKs are not effec ted by this input. / T rue c loc k of differential pus h-
pull SRC pair.
31
VDDSRC
PWR
Supply for SRC PLL, 3.3V nominal
32
SRCC6
O UT
Complement c loc k of low power differential SRC c loc k pair.
33
SRCT6
O UT
True c loc k of low power differential SRC c loc k pair.
34
G NDSRC
PWR
G round pin for the SRC outputs
35
SRCC7/CR#_E
I/O
Complement c loc k of differential pus h-pull SRC c loc k pair. / Cloc k Reques t c ontrol E for SRC6 pair. T he power-up default is
SRC7#, but this pin may als o be us ed as a Cloc k Reques t c ontrol of SRC6 v ia SMBus . Before c onfiguring this pin as a Cloc k
Reques t Pin, the SRC7 output pair mus t firs t be dis abled in by te 3, bit 3 of SMBus c onfiguration s pac e . After the SRC output is
dis abled (high-Z), the pin c an then be s et to s erv e as a Cloc k Reques t for SRC6 pair us ing by te 6, bit 7 of SMBus c onfiguration
s pac e
By te 6, bit 7
0 = SRC7# enabled (default)
1= CRE# enabled.
36
SRCT7/CR#_F
I/O
True c loc k of differential pus h-pull SRC c loc k pair/ Cloc k Reques t c ontrol 8 for SRC8 pair
The power-up default is SRC7, but this pin may als o be us ed as a Cloc k Reques t c ontrol of SRC8 v ia SMBus . Before c onfiguring
this pin as a Cloc k Reques t Pin, the SRC7 output pair mus t firs t be dis abled in by te 3, bit 3 of SMBus c onfiguration s pac e After the
SRC output is dis abled (high-Z), the pin c an then be s et to s erv e as a Cloc k Reques t for SRC8 pair us ing by te 6, bit 6 of SMBus
c onfiguration s pac e.
By te 6, bit 6
0 = SRC7# enabled (default)
1 = CRF# enabled.
37
VDDSRC_IO
PWR
Power s upply for SRC c loc k s . 0.8V nominal from s ourc e/emitter of ex ternal pas s trans is tor
38
CPUC2_IT P/SRCC8
O UT
Complement c loc k of low power differential CPU2/Complement c loc k of differential SRC pair. The func tion of this pin is determined
by the latc hed input v alue on pin 7, PCIF5/ITP_EN on powerup. T he func tion is as follows :
Pin 7 latc hed input Value
0 = SRC8#
1 = ITP#
39
CPUT2_IT P/SRCT8
O UT
True c loc k of low power differential CPU2/True c loc k of differential SRC pair. The func tion of this pin is determined by the latc hed
input v alue on pin 7, PCIF5/ITP_EN on powerup. T he func tion is as follows :
Pin 7 latc hed input Value
0 = SRC8
1 = ITP
40
VO UT
PWR
O P Amp c omparator output. T his pin driv es the bas e/gate of the ex ternal pas s trans is tor
41
VDDCPU_IO
PWR
Supply for CPU c loc k s . 0.8V nominal from s ourc e/emitter of ex ternal pas s trans is tor
42
CPUC1_F
O UT
Complementary c loc k of low power differential pus h-pull CPU output. This CPU c loc k is free running during iAMT.
43
CPUT1_F
O UT
True c loc k of differential pus h-pull CPU c loc k pair. T his c loc k is free running during iAMT.
44
G NDCPU
PWR
G round pin for the CPU outputs
45
CPUC0
O UT
Complement c loc k of low power differential CPU c loc k pair.
46
CPUT0
O UT
True c loc k of low power differential CPU c loc k pair.
47
VDDCPU
PWR
Supply for CPU PLL, 3.3V nominal
48
CK_PWRG D/PD#
IN
Notifies CK505 to s ample latc hed inputs , or iAMT entry /ex it, or PWRDWN# mode
49
F SLB/T EST _MO DE
IN
3.3V tolerant input for CPU frequenc y s elec tion. Refer to input elec tric al c harac teris tic s for Vil_FS and Vih_F S v alues .
TEST_MO DE is a real time input to s elec t between Hi-Z and REF /N div ider mode while in tes t mode. Refer to Tes t Clarific ation
Table.
50
G NDREF
PWR
G round pin for the REF outputs .
51
X2
O UT
Cry s tal output, Nominally 14.318MHz
52
X1
IN
Cry s tal input, Nominally 14.318MHz .
53
VDDREF
PWR
Ref, XTAL power s upply , nominal 3.3V
54
REF 0/F SLC/TEST_SEL
I/O
14.318 MHz referenc e c loc k ./ 3.3V tolerant input for CPU frequenc y s elec tion. Refer to input elec tric al c harac teris tic s for Vil_F S
and Vih_F S v alues . /TEST_Sel: 3-lev el latc hed input to enable tes t mode. Refer to Tes t Clarific ation T able
55
SDATA
I/O
Data pin for SMBus c irc uitry , 5V tolerant.
56
SCLK
IN
Cloc k pin of SMBus c irc uitry , 5V tolerant.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9LP525BG-2LF | 功能描述:時鐘合成器/抖動清除器 CK505 PCIe Gen2 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LP525BG-2LFT | 功能描述:時鐘合成器/抖動清除器 CK505 PCIe Gen2 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LPC01781 | 制造商:Denon 功能描述:BUTTON POWERAVR-600 |
| 9LPH02002 | 制造商:Denon 功能描述:DISPLAY SHEETD-C30 |
| 9LPH02481 | 制造商:Denon 功能描述:F/PANELD-C30 |
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