參數(shù)資料
型號(hào): 9FGP202AKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 33.33 MHz, OTHER CLOCK GENERATOR, PQCC40
封裝: ROHS COMPLIANT, PLASTIC, MLF-40
文件頁數(shù): 7/18頁
文件大?。?/td> 137K
代理商: 9FGP202AKLFT
15
Integrated
Circuit
Systems, Inc.
ICS9FGP202A
1339C—09/14/09
SMBus Table: CPU PLL VCO Frequency Control Register
Byte 11
Name
Control Function
Type0
1
PWD
Bit 7
N Div8
N Divider Prog bit 8
RW
X
Bit 6
N Div 9
N Divider Prog bit 9
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
SMBus Table: CPU PLL VCO Frequency Control Register
Byte 12
Name
Control Function
Type0
1
PWD
Bit 7
N Div7
RW
X
Bit 6
N Div6
RW
X
Bit 5
N Div5
RW
X
Bit 4
N Div4
RW
X
Bit 3
N Div3
RW
X
Bit 2
N Div2
RW
X
Bit 1
N Div1
RW
X
Bit 0
N Div0
RW
X
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte 13
Name
Control Function
Type0
1
PWD
Bit 7
SSP7
RW
X
Bit 6
SSP6
RW
X
Bit 5
SSP5
RW
X
Bit 4
SSP4
RW
X
Bit 3
SSP3
RW
X
Bit 2
SSP2
RW
X
Bit 1
SSP1
RW
X
Bit 0
SSP0
RW
X
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte 14
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
SMBus Table: DOT PLL VCO Frequency Control Register
Byte 15
Name
Control Function
Type0
1
PWD
Bit 7
N Div8
N Divider Prog bit 8
RW
X
Bit 6
N Div9
N Divider Prog bit 9
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
SMBus Table: DOT PLL VCO Frequency Control Register
Byte 16
Name
Control Function
Type0
1
PWD
Bit 7
N Div7
RW
X
Bit 6
N Div6
RW
X
Bit 5
N Div5
RW
X
Bit 4
N Div4
RW
X
Bit 3
N Div3
RW
X
Bit 2
N Div2
RW
X
Bit 1
N Div1
RW
X
Bit 0
N Div0
RW
X
N Divider Programming b(7:0)
The decimal representation of M and N
Divier in Byte 11 and 12 will configure
the VCO frequency. Default at power
up = latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
Pin #
-
The decimal representation of M and N
Divier in Byte 17 and 18 will configure
the VCO frequency. Default at power
up = Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
N Divider Programming b(7:0)
The decimal representation of M and N
Divier in Byte 17 and 18 will configure
the VCO frequency. Default at power
up = Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
The decimal representation of M and N
Divier in Byte 11 and 12 will configure
the VCO frequency. Default at power
up = latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
-
Pin #
-
Spread Spectrum Programming
b(7:0)
-
Spread Spectrum Programming
b(14:8)
-
Pin #
-
Pin #
-
M Divider Programming bits
-
Pin #
-
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Reserved
M Divider Programming bits
-
Pin #
-
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