參數(shù)資料
型號: 9FGP202AKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 33.33 MHz, OTHER CLOCK GENERATOR, PQCC40
封裝: ROHS COMPLIANT, PLASTIC, MLF-40
文件頁數(shù): 11/18頁
文件大?。?/td> 137K
代理商: 9FGP202AKLFT
2
Integrated
Circuit
Systems, Inc.
ICS9FGP202A
1339C—09/14/09
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1
GND
PWR
Ground pin.
2
VDD96
PWR
Power pin for the DOT96 clocks, nominal 3.3V
3
DOT96SST
OUT
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
4
DOT96SSC
OUT
Complement clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
5
OE_96
IN
Active high input for enabling 96Hz outputs.
1 = enable output(s), 0 = tri-state output(s)
6OE_CPU
IN
Active high input for enabling CPU DIFF pairs.
1 = enable output(s), 0 = tri-state output(s)
7
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
8
CPUCLKC0
OUT
Complementary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
9
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
10
GNDCPU
PWR
Ground pin for the CPU outputs
11
IREF
OUT
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the appropriate current.
475 ohms is the standard value.
12
VDD32K
PWR
Power pin for the 32.768KHz outputs, nominal 3.3V
13
32.768KHz
OUT
32.768KHz clock output
14
GND32K
PWR
Ground pin for the 32.768KHz outputs
15
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
16
25MHz_0
OUT
25MHz clock output, 3.3V
17
25MHZ_1
OUT
25MHz clock output, 3.3V
18
GNDREF
PWR
Ground pin for the REF outputs.
19
X1_25
IN
Crystal input, Nominally 25.00MHz.
20
X2_25
OUT
Crystal output, Nominally 25.00MHz.
21
GND33
PWR
Ground pin for the 33.33MHz outputs
22
33.33MHZ/**SMBADR
I/O
33.33MHz clock output / SMBus address select bit.
23
VDD33
PWR
Power pin for the 33.33MHz outputs, nominal 3.3V
24
RMII7
OUT
3.3V RMII clock output
25
RMII6
OUT
3.3V RMII clock output
26
VDDRMII
PWR
3.3V power pin for the RMII clocks.
27
GNDRMII
PWR
Ground pin for the 3V50 outputs
28
RMII5
OUT
3.3V RMII clock output
29
RMII4
OUT
3.3V RMII clock output
30
OE_RMIIB
IN
Active high input for enabling RMII(7:4) outputs.
1 = enable output(s), 0 = low
31
OE_RMIIA
IN
Active high input for enabling RMII(3:0) outputs.
1 = enable output(s), 0 = low
32
RMII3
OUT
3.3V RMII clock output
33
RMII2
OUT
3.3V RMII clock output
34
VDDRMII
PWR
3.3V power pin for the RMII clocks.
35
GNDRMII
PWR
Ground pin for the 3V50 outputs
36
RMII1
OUT
3.3V RMII clock output
37
RMII0
OUT
3.3V RMII clock output
38
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
39
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
40
VttPwr_GD/PD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid
and are ready to be sampled. This is an active high input. / Asynchronous active low input pin
used to power down the device into a low power state.
Pin Description
相關(guān)PDF資料
PDF描述
9G100 ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4
9G125S ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4
9G125 ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4
9G150 ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4
9G35 ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4
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