參數(shù)資料
型號(hào)： 9DB1904BKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
封裝： ROHS COMPLIANT, PLASTIC, MLF-72
文件頁(yè)數(shù)： 18/18頁(yè)
文件大小： 173K
代理商： 9DB1904BKLFT
IDT
19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
9
Electrical Characteristics - Phase Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
tjphPCIeG1
PCIe Gen 1
35
86
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.2
3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.5
3.1
ps
(rms)
1,2
tjphQPI_SMI
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.30
0.5
ps
(rms)
1,5
tjphPCIeG1
PCIe Gen 1
3
10
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.01
0.3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.8
1.3
ps
(rms)
1,2,6
tjphQPI_SMI
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.12
0.3
ps
(rms)
1,5,6
1 Applies to all outputs.
6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3
tjphPCIeG2
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Subject to final radification by PCI SIG.
Phase Jitter, PLL Mode
Additive Phase Jitter,
Bypass mode
Clock Periods - Differential Outputs with Spread Spectrum Disabled
1 Clock
1us
0.1s
1us
1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
100.00
9.94900
9.99900
10.00000
10.00100
10.05100
ns
1,2
133.33
7.44925
7.49925
7.50000
7.50075
7.55075
ns
1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1 Clock
1us
0.1s
1us
1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
99.75
9.94906
9.99906
10.02406
10.02506
10.02607
10.05107
10.10107
ns
1,2
133.00
7.44930
7.49930
7.51805
7.51880
7.51955
7.53830
7.58830
ns
1,2
1Guaranteed by design and characterization, not 100% tested in production.
DIF
Notes
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ
accuracy requirements. The 9DB1904 itself does not contribute to ppm error.
Measurement Window
Units
SSC ON
Center
Freq.
MHz
Notes
Measurement Window
Units
SSC OFF
Center
Freq.
MHz
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