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參數(shù)資料
| 型號： | 9DB102AGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PDSO20 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 223K |
| 代理商： | 9DB102AGILF |
IDTTM
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV J 01/15/10
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
5
Electrical Characteristics - PLL Parameters
TA = Tambient; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
Min
Typ
Max
Units
Notes
PLL Jitter Peaking
jpeak-hibw
(PLL_BW = 1)
0
1
2.5
dB
1,4
PLL Jitter Peaking
jpeak-lobw
(PLL_BW = 0)
0
1
2
dB
1,4
PLL Bandwidth
pllHIBW
(PLL_BW = 1)
2
2.5
3
MHz
1,5
PLL Bandwidth
pllLOBW
(PLL_BW = 0)
0.4
0.5
1
MHz
1,5
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
40
108
ps
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=1)
2.7
3.1
ps rms
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
2.2
3.1
ps rms
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
1.3
3
ps rms
1,2,3
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
Jitter, Phase
tjphasePLL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB102AGLF | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102AFLFT | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102AFLF | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102AGLFT | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102BFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB102BFILF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Two Output Differential Buffer for PCIe Gen1 & Gen2 |
| 9DB102BFILFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Two Output Differential Buffer for PCIe Gen1 & Gen2 |
| 9DB102BFLF | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB102BFLFT | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB102BGILF | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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