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參數(shù)資料
| 型號： | 9DB102AGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PDSO20 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 223K |
| 代理商： | 9DB102AGILF |
IDTTM
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV J 01/15/10
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
8
General SMBus serial interface information for the ICS9DB102
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D4
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D5
(h)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X
B
yt
e
Index Block Write Operation
Slave Address D4(h)
Beginning Byte = N
WRite
starT bit
Controller (Host)
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
PstoP bit
ICS (Slave/Receiver)
Controller (Host)
X
Byte
ACK
Data Byte Count = X
ACK
Slave Address D5(h)
Index Block Read Operation
Slave Address D4(h)
Beginning Byte = N
ACK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB102AGLF | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102AFLFT | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102AFLF | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102AGLFT | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102BFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB102BFILF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Two Output Differential Buffer for PCIe Gen1 & Gen2 |
| 9DB102BFILFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Two Output Differential Buffer for PCIe Gen1 & Gen2 |
| 9DB102BFLF | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB102BFLFT | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB102BGILF | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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