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參數(shù)資料
| 型號： | 9601-01 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 2200 MHz UltraCMOS⑩ Integer-N PLL for Rad Hard Applications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 257K |
| 代理商： | 9601-01 |
Product Specification
PE9601
Page 12 of 14
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0025-05
│ UltraCMOS RFIC Solutions
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
Reserved**
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming as directed by the
Bmode and
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
Prescaler output
Drives the raw internal prescaler output (fmain) onto the Dout output.
Bit 7
fp, fc OE
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_D pulses “high”. If the divided reference leads
the divided VCO in phase or frequency (fr leads
fp), PD_U pulses “high”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
The signals from the phase detector couple di-
rectly to a charge pump. PD_U controls a current
source at pin CP with constant amplitude and
pulse duration approximately the same as PD_U.
PD_D similarly drives a current sink at pin CP.
The current pulses from pin CP are low pass fil-
tered externally and then connected to the VCO
tune voltage. PD_U pulses result in a current
source, which increases the VCO frequency and
PD_D results in a current sink, which decreases
VCO frequency.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “OR” of PD_U and
PD_D waveforms, which is driven through a series
2 k ohm resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “NOR”
function of PD_U and PD_D.
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