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參數(shù)資料
| 型號： | 9601-01 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 2200 MHz UltraCMOS⑩ Integer-N PLL for Rad Hard Applications |
| 中文描述： | PHASE LOCKED LOOP, CQCC44 |
| 封裝： | CERAMIC, QFJ-44 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 257K |
| 代理商： | 9601-01 |
Product Specification
PE9601
Page 8 of 14
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0025-05
│ UltraCMOS RFIC Solutions
The PE9601 consists of a prescaler, counters, a
phase detector, a charge pump and control logic.
The dual modulus prescaler divides the VCO
frequency by either 10 or 11, depending on the
value of the modulus select. Counters “R” and “M”
divide the reference and prescaler output,
respectively, by integer values stored in a 20-bit
register. An additional counter (“A”) is used in the
modulus select logic. The phase-frequency
detector generates up and down frequency control
signals, which are implemented as a pulse width
modulated current by the charge pump. The
control logic includes a selectable chip interface.
Data can be written via serial bus, parallel bus, or
hardwired direct to the pins. There are also
various operational and test modes and lock
detect.
Functional Description
Figure 5. Functional Block Diagram
Control
Logic
Modulus
Select
10/11
Prescaler
M Counter
(9-bit)
R Counter
(6-bit)
Phase
Detector
2 k
fc
PD_U
PD_D
LD
Cext
fp
R(5:0)
M(8:0)
A(3:0)
D(7:0)
Sdata
Control
Pins
fr
Fin
Charge
Pump
C
Fin
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