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參數(shù)資料
| 型號： | 95V857AL-130T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 138K |
| 代理商： | 95V857AL-130T |
5
ICS95V857 -XXX
0674R—12/15/04
Recommended Operating Condition (see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDD, AVDD
2.3
2.5
2.7
V
CLKT, CLKC, FB_INC
0.4
VDD/2 - 0.18
V
PD#
-0.3
0.7
V
CLKT, CLKC, FB_INC
VDD/2 + 0.18
2.1
V
PD#
1.7
VDD + 0.6
V
DC input signal voltage
(note 2)
VIN
-0.3
VDD + 0.3
V
DC - CLKT, FB_INT
0.36
VDD + 0.6
V
AC - CLKT, FB_INT
0.7
VDD + 0.6
V
Output differential cross-
voltage (note 4)
VOX
VDD/2 - 0.15
VDD/2 + 0.15
V
Input differential cross-
voltage (note 4)
VIX
VDD/2 - 0.2
VDD/2
VDD/2 + 0.2
V
High level output
current
IOH
-6.4
mA
Low level output current
IOL
5.5
mA
Operating free-air
temperature
TA
085
°C
Differential input signal
voltage (note 3)
VID
Low level input voltage
VIL
High level input voltage
VIH
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of VDD and is the
voltage at which the differential signal must be crossing.
相關PDF資料 |
PDF描述 |
|---|---|
| 95V857AL-130T-LF | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 95V857AL-130LF-T | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 95V857AG-130T-LF | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 95V857AGILF-T | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 95V857ALILF-T | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 95V857ALLF | 功能描述:時鐘驅動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 95V857ALLFT | 功能描述:時鐘驅動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 95V857ALT | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 45MHz to 233MHz 48-Pin TVSOP T/R |
| 95V857CGLF | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 45MHz to 233MHz 48-Pin TSSOP Tube |
| 95VLP857AGLF | 功能描述:IC CLK BUF DDR 233MHZ 1CIRC 制造商:idt, integrated device technology inc 系列:- 包裝:管件 零件狀態(tài):過期 PLL:是 主要用途:存儲器，DDR 輸入:LVCMOS 輸出:SSTL-2 電路數(shù):1 比率 - 輸入:輸出:1：10 差分 - 輸入:輸出:是/是 頻率 - 最大值:233MHz 電壓 - 電源:2.3 V ~ 2.7 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商器件封裝:48-TSSOP 標準包裝:39 |
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