參數(shù)資料
型號(hào)： 95V857AL-130T
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝： 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48
文件頁(yè)數(shù)： 10/13頁(yè)
文件大?。?/td> 138K
代理商： 95V857AL-130T
6
ICS95V857-XXX
0674R—12/15/04
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V+0.2V @ 25
oC
45
233
MHz
Application Frequency
Range
freqApp
2.5V+0.2V @ 25
oC
95
220
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
15
s
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
3.5
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
3.5
ns
Output enable time
tEN
PD# to any output
3
ns
Output disable time
tdis
PD# to any output
3
ns
Period jitter
Tjit (per)
100MHz to 200MHz
-30
30
ps
Half-period jitter
t(jit_hper)
100MHz to 200MHz
-75
75
ps
Input clock slew rate
tsl(i)
14
V/ns
Output clock slew rate
tsl(o)
12
V/ns
Cycle to Cycle Jitter
1
Tcyc-Tcyc
100MHz to 200MHz
-50
50
ps
Static Phase Offset
t(static phase offset)
4
-50
0
50
ps
Output to Output Skew
Tskew
40
ps
相關(guān)PDF資料
PDF描述
95V857AL-130T-LF 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
95V857AL-130LF-T 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
95V857AG-130T-LF 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
95V857AGILF-T PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
95V857ALILF-T PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
95V857ALLF 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
95V857ALLFT 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
95V857ALT 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 45MHz to 233MHz 48-Pin TVSOP T/R
95V857CGLF 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 45MHz to 233MHz 48-Pin TSSOP Tube
95VLP857AGLF 功能描述:IC CLK BUF DDR 233MHZ 1CIRC 制造商:idt, integrated device technology inc 系列:- 包裝:管件 零件狀態(tài):過期 PLL:是 主要用途:存儲(chǔ)器，DDR 輸入:LVCMOS 輸出:SSTL-2 電路數(shù):1 比率 - 輸入:輸出:1：10 差分 - 輸入:輸出:是/是 頻率 - 最大值:233MHz 電壓 - 電源:2.3 V ~ 2.7 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商器件封裝:48-TSSOP 標(biāo)準(zhǔn)包裝:39
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