參數(shù)資料
型號(hào): 95V850AGLF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 0.240 INCH, LEAD FREE, MO-153, TSSOP-48
文件頁數(shù): 6/10頁
文件大?。?/td> 151K
代理商: 95V850AGLF-T
5
ICS95V850
0458G—11/21/08
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
5.5
ns
Period jitter
Tjit (per)
100MHz to 200MHz
-30
30
ps
Half-period jitter
t(jit_hper)
100MHz to 200MHz
-75
30
ps
Input clock slew rate
tsl(i)
14
V/ns
Output clock slew rate
tsl(o)
12.5
V/ns
Cycle to Cycle Jitter
1
Tcyc-Tcyc
100MHz to 200MHz
60
ps
Phase error
t(phase error)
4
-50
0
50
ps
Output to Output Skew
Tskew
60
ps
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