- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄25526 > 95V2F857AHLFT (INTEGRATED DEVICE TECHNOLOGY INC) 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 PDF資料下載
參數(shù)資料
| 型號(hào)： | 95V2F857AHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 95V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 |
| 封裝： | LEAD FREE, MO-205, MO-225, BGA-56 |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大小： | 146K |
| 代理商： | 95V2F857AHLFT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)
6
ICS95V2F857A
1065A—0 2/03/05
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V+0.2V @ 25
oC
45
233
MHz
Application Frequency
Range
freqApp
2.5V+0.2V @ 25
oC
95
220
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
15
s
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
CLK_IN to any output
3.5
ns
High-to low level propagation
delay time
tPLL
1
CLK_IN to any output
3.5
ns
Output enable time
tEN
PD# to any output
3
ns
Output disable time
tdis
PD# to any output
3
ns
Period jitter
Tjit (per)
100MHz to 200MHz
-30
30
ps
Half-period jitter
t(jit_hper)
100MHz to 200MHz
-100
100
ps
Input clock slew rate
tsl(i)
14
V/ns
Output clock slew rate
tsl(o)
12
V/ns
Cycle to Cycle Jitter
1
Tcyc-Tcyc
100MHz to 200MHz
-50
50
ps
Static Phase Offset
t(static phase offset)
4
-50
0
50
ps
Output to Output Skew
Tskew
40
ps
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 95V842AFILF-T | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 95V842YFLF-T | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 95V842YFILF | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 95V842AFLF | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 95V842AFLF-T | 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 95V2F857AKLF | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK DRVR SGL 45MHZ TO 233MHZ 40PIN VFQFPN - Trays 制造商:Integrated Device Technology Inc 功能描述:IDT 95V2F857AKLF PLL |
| 95V2F857AKLFT | 制造商:Integrated Device Technology Inc 功能描述:40 VFQFPN (GREEN) - Tape and Reel |
| 95V842AFILF | 制造商:Integrated Device Technology Inc 功能描述:16 QSOP (GREEN) - Bulk |
| 95V842AFILFT | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 33MHZ TO 333MHZ 16QSOP - Tape and Reel |
| 95V842AFLF | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。