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參數(shù)資料
| 型號： | 952601EGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH, GREEN, MO-118, SSOP-56 |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 952601EGLFT |
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21
Integrated
Circuit
Systems, Inc.
ICS952601
0701I—05/04/05
The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and
SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
SRC_Stop = Driven, SRC_Pwrdwn = Driven
PCI_Stop#
1.8mS
PWRDWN#
PCI (Free Running)
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output
clock (assuming clock's OE bit is set to "1")
SRC Clock Tristate Timing
SRC_Stop = Tristate, Pwrdwn = Tristate
PCI_Stop#
1.8mS
PWRDWN#
PCI (Free Running)
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of
PCI_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
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