參數(shù)資料
型號(hào)： 952601EGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, 0.025 INCH, GREEN, MO-118, SSOP-56
文件頁(yè)數(shù)： 11/27頁(yè)
文件大?。?/td> 321K
代理商： 952601EGLFT
19
Integrated
Circuit
Systems, Inc.
ICS952601
0701I—05/04/05
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU Clock Tristate Timing
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
相關(guān)PDF資料
PDF描述
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