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參數(shù)資料
| 型號(hào)： | 951901AF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-48 |
| 文件頁(yè)數(shù)： | 9/21頁(yè) |
| 文件大小： | 206K |
| 代理商： | 951901AF |
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17
ICS951901
0670B—07/15/04
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power
operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS94209. All other clocks will
continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the SDRAM clocks inside the ICS94209.
3. All other clocks continue to run undisturbed.
相關(guān)PDF資料 |
PDF描述 |
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| 951901AFLFT | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 951 | WIRE TERMINAL |
| 952001AF | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 952001AFLF | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 952001AFLFT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 951901AFLF | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Frequency Generator Dual 48-Pin SSOP Tube |
| 951901AFLFT | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Frequency Generator Dual 48-Pin SSOP T/R |
| 951902 | 制造商:Weidmuller 功能描述:WPG-M25, CABLE GLAND, PA,BLA -EA - Bulk |
| 951903 | 制造商:Weidmuller 功能描述:WPG-M32, CABLE GLAND, PA,BLA -EA - Bulk |
| 951904 | 制造商:Weidmuller 功能描述:WPG-M40, CABLE GLAND, PA,BLA -EA - Bulk |
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