- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24862 > 950211BFLF (INTEGRATED DEVICE TECHNOLOGY INC) 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 PDF資料下載
參數(shù)資料
| 型號(hào)： | 950211BFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, GREEN, MO-118, SSOP-56 |
| 文件頁(yè)數(shù)： | 10/23頁(yè) |
| 文件大?。?/td> | 214K |
| 代理商： | 950211BFLF |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)
18
Integrated
Circuit
Systems, Inc.
ICS950211
0465E—05/17/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
P
O
T
S
_
U
P
CT
U
P
CC
U
P
C
1l
a
m
r
o
Nl
a
m
r
o
N
0t
l
u
M
*
f
e
r
it
a
o
l
F
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 08053C103KA72A | General Specifications |
| 950211BFLFT | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 950211BFT | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 08053C103KA74A | General Specifications |
| 950218AFLFT | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 950211BFLFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 950211BGLF | 制造商:Integrated Device Technology Inc 功能描述:IDT 950211BGLF Phased Locked Loop (PLL) |
| 950-212 | 制造商:Mitutoyo Corporation 功能描述:SPRING DIVIDER; Instrument Type:Spring Divider; Measuring Range Max:6" ;RoHS Compliant: NA |
| 9502-12INX180YDS | 制造商:3M Electronic Products Division 功能描述:70006170149 |
| 950-213 | 制造商:Mitutoyo Corporation 功能描述:SPRING DIVIDER, 8" |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。