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參數(shù)資料
| 型號(hào)： | 94302-01 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | 衰減器 |
| 英文描述： | 50 ヘ RF Digital Step Attenuator For Rad-Hard Space Applications 6-bit, 31.5 dB, DC - 4.0 GHz |
| 中文描述： | 0 MHz - 4000 MHz RF/MICROWAVE VARIABLE ATTENUATOR, 2.75 dB INSERTION LOSS-MAX |
| 封裝： | CERAMIC, QFP-28 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | 94302-01 |
Product Specification
PE94302
Page 4 of 6
2005-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0186-04
│ UltraCMOS RFIC Solutions
Table 6. 6-Bit Attenuator Serial Programming
Register Map
Table 8. Parallel Interface AC Characteristics
Figure 5. Parallel Interface Timing Diagram
Table 7. Serial Interface AC Characteristics
Figure 4. Serial Interface Timing Diagram
LE
Clock
Data
MSB
LSB
t
LESUP
t
SDSUP
t
SDHLD
t
LEPW
B5
B4
B3
B2
B1
B0
C16
C8C4C2
C1
C0.5
↑↑
LSB (last in)
MSB (first in)
t
PDSUP
t
PDHLD
Parallel Data
C16:C0.5
LE
t
LEPW
Symbol
Parameter
Min
Max
Unit
fClk
Serial data clock
frequency (Note 1)
10
MHz
tClkH
Serial clock HIGH time
30
ns
tClkL
Serial clock LOW time
30
ns
tLESUP
LE set-up time after last
clock falling edge
10
ns
tLEPW
LE minimum pulse width
30
ns
tSDSUP
Serial data set-up time
before clock rising edge
10
ns
tSDHLD
Serial data hold time
after clock falling edge
10
ns
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked at
10 MHz to verify fclk specification.
Symbol
Parameter
Min
Max
Unit
tLEPW
LE minimum pulse width
10
ns
tPDSUP
Data set-up time before
rising edge of LE
10
ns
tPDHLD
Data hold time after
falling edge of LE
10
ns
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
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