- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄164768 > 94302-01 (PEREGRINE SEMICONDUCTOR CORP) 50 ヘ RF Digital Step Attenuator For Rad-Hard Space Applications 6-bit, 31.5 dB, DC - 4.0 GHz PDF資料下載
參數(shù)資料
| 型號： | 94302-01 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | 衰減器 |
| 英文描述： | 50 ヘ RF Digital Step Attenuator For Rad-Hard Space Applications 6-bit, 31.5 dB, DC - 4.0 GHz |
| 中文描述： | 0 MHz - 4000 MHz RF/MICROWAVE VARIABLE ATTENUATOR, 2.75 dB INSERTION LOSS-MAX |
| 封裝： | CERAMIC, QFP-28 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 374K |
| 代理商： | 94302-01 |
Product Specification
PE94302
Page 3 of 6
Document No. 70-0186-04
│ www.psemi.com
2005-2008 Peregrine Semiconductor Corp. All rights reserved.
Programming Options
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE94302. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of six CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The parallel interface timing requirements are
defined by Figure 5 (Parallel Interface Timing
Diagram), Table 8 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For
latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 5) to latch new attenuation state into
device.
For
direct parallel programming, the Latch Enable
(LE) should be either pulled high or floated (see
Table 2, note 2). Changing attenuation state control
values will change device state to new attenuation.
Direct Mode is ideal for manual control of the device
(using hardwire, switches, or jumpers).
P/S
C16
C8
C4
C2
C1
C0.5
Attenuation
State
0
Reference Loss
0
1
0.5 dB
0
1
0
1 dB
0
1
0
2 dB
0
1
0
4 dB
0
1
0
8 dB
0
1
0
16 dB
0
1
31.5 dB
Table 5. Truth Table
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
Serial Interface
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch.
It is
controlled by three CMOS-compatible signals
: Data,
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator.
When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered.
The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 4 (Serial Interface Timing Diagram) and Table
7 (Serial Interface AC Characteristics).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 94302-11 | 50 ヘ RF Digital Step Attenuator For Rad-Hard Space Applications 6-bit, 31.5 dB, DC - 4.0 GHz |
| 94337-000 | 68 CONTACT(S), MALE, RIGHT ANGLE PCMCIA CONNECTOR, SOLDER |
| 9444-7044 | 44 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET |
| 9444-7644 | 44 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET |
| 9436-6006 | 36 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 943020200 | 制造商: 功能描述: 制造商:Texas Instruments 功能描述: 制造商:undefined 功能描述: |
| 9430208605 | 制造商:Denon Electronics 功能描述:CADSDL003XA LOADER ASSY 制造商:DENON ELECTRONICS 功能描述:CADSDL003XA LOADER ASSY |
| 94302-11 | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:50 ohm RF Digital Step Attenuator For Rad-Hard Space Applications 6-bit, 31.5 dB, DC - 4.0 GHz |
| 9-430-2750 | 制造商:Keystone Electronics Corp 功能描述: |
| 943028-1 | 制造商:TE CONNECTIVITY 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。