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參數(shù)資料
| 型號： | 93CS46 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1K 64 x 16 SERIAL MICROWIRE EEPROM |
| 中文描述： | 每1000 64 × 16系列MICROWIRE的EEPROM的 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 124K |
| 代理商： | 93CS46 |
POWER-ON DATA PROTECTION
In orderto prevent datacorruption and inadvertent
write operations during power up, a Power On
Reset(POR)circuit resetsallinternalprogramming
circuitry and sets the device in the Write Disable
mode. When V
CC
reaches its functionalvalue, the
deviceisproperlyreset (in the Write Disablemode)
and is ready to decode and execute an incoming
instruction. A stable V
CC
must be applied before
any logic signal.
INSTRUCTIONS
The ST93CS46/47 has eleven instructions, as
shown in Table 6. Each instruction is preceded by
the rising edge of the signal applied on the Chip
Select(S) input(assuming that the Clock Cis low),
followed by a ’1’ read on D input during the rising
edge of the clock C. The op-codes of the instruc-
tions are made up of the 2 following bits. Some
instructionsuse onlythese first twobits,othersuse
also the first two bits of the addressfield to define
the op-code. The address field is six bits long
(A5-A0).
The ST93CS46/47 is fabricated inCMOS technol-
ogyandisthereforeableto run from zeroHz (static
inputsignals)up to themaximumratings (specified
in Table 5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). Whena READinstruction
is received, the instruction and address are de-
codedand thedata from thememory is transferred
intoanoutputshiftregister.Adummy’0’bitisoutput
first followedby the 16 bitword with the MSBfirst.
Instruction
Description
W
Pin
(1)
PRE
Pin
Op
Code
Address
(1)
Data
Additional
Information
READ
Read Data from Memory
X
’0’
10
A5-A0
Q15-Q0
WRITE
Write Data to Memory
’1’
’0’
01
A5-A0
D15-D0
Write is executed if
the address is not
inside the Protected
area
PAWRITE
Page Write to Memory
’1’
’0’
11
A5-A0
D15-D0
Write is executed if
all the addresses
are not inside the
Protected area
WRALL
Write All Memory
’1’
’0’
00
01XXXX
D15-D0
Write all data if the
Protect Register is
cleared
WEN
Write Enable
’1’
’0’
00
11XXXX
WDS
Write Disable
X
’0’
00
00XXXX
PRREAD
Protect Register Read
X
’1’
10
XXXXXX
Q8-Q0
Data Output =
Protect Register
content + Protect
Flag bit
PRWRITE
Protect Register Write
’1’
’1’
01
A5-A0
Data above
specifiedaddress
A5-A0 are protected
PRCLEAR
Protect Register Clear
’1’
’1’
11
111111
Protect Flag is also
cleared (cleared
Flag = 1)
PREN
Protect Register Enable
’1’
’1’
00
11XXXX
PRDS
Protect Register Disable
’1’
’1’
00
000000
OTPbit is set
permanently
Note:
1. X =don’t care bit.
Table 6. InstructionSet
6/16
ST93CS46, ST93CS47
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|---|---|
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| 93L08DMQB | Dual 4-Bit Latch |
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