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參數(shù)資料
| 型號： | 93CS46 |
| 廠商： | 意法半導體 |
| 英文描述： | 1K 64 x 16 SERIAL MICROWIRE EEPROM |
| 中文描述： | 每1000 64 × 16系列MICROWIRE的EEPROM的 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 124K |
| 代理商： | 93CS46 |
Accessing the ProtectRegisteris done by execut-
ing the followingsequence:
– WEN: execute the Write Enableinstruction,
– PREN: executethe PRENinstruction,
– PRWRITE, PRCLEAR or PRDS:the protection
then may be defined, in terms of size of the
protected area (PRWRITE, PRCLEAR) and
may be set permanently(PRDS instruction).
Protect RegisterRead
The Protect Register Read instruction (PRREAD)
outputs on the Data Output Q the content of the
Protect Register, followed by the Protect Flag bit.
The Protect Register Enable pin (PRE) must be
driven Highbeforeand duringthe instruction. As in
the Read instructiona dummy ’0’ bit is output first.
Since it is not possible to distinguishif the Protect
Registeris cleared(all 1’s) or if it is written with all
1’s, user must check the Protect Flag status (and
not the Protect Register content) to ascertainthe
settingof the memory protection.
Protect RegisterEnable
The ProtectRegister Enableinstruction(PREN) is
used to authorize the use of further PRCLEAR,
PRWRITE and PRDS instructions. The PREN
insruction does not modify the Protect Flag bit
value.
Note: A Write Enable (WEN) instruction must be
executed before the Protect Enable instruction.
Both the Protect Enable (PRE) and Write Enable
(W)inputpinsmust beheldHighduringtheinstruc-
tion execution.
Protect RegisterClear
The Protect RegisterClear instruction(PRCLEAR)
clears the addressstoredin theProtect Register to
all 1’s, and thus enables the execution of WRITE
and WRALL instructions. The Protect Register
Clear executionclears the ProtectFlag to ’1’. Both
the Protect Enable (PRE) and Write Enable (W)
input pins must be driven High during the instruc-
tion execution.
Note: A PREN instruction must immediately pre-
cede the PRCLEARinstruction.
Protect RegisterWrite
The Protect Register Write instruction(PRWRITE)
is used to write into the Protect Register the ad-
dress of the first word to be protected. After the
PRWRITE instruction execution, all memory loca-
tions equalto andabovethespecifiedaddress,are
protectedfrom writing. The Protect Flagbitis set to
’0’, it can be read with Protect Register Read
instruction. Both the Protect Enable (PRE) and
Write Enable (W) input pins must be driven High
during the instruction execution.
Note: A PREN instruction must immediately pre-
cede the PRWRITE instruction, but it is not neces-
sary to execute first aPRCLEAR.
ProtectRegister Disable
The Protect Register Disable instruction sets the
One TimeProgrammablebit(OTPbit).TheProtect
RegisterDisableinstruction(PRDS) isaONETIME
ONLYinstruction which latchesthe ProtectRegis-
ter content,this content is therefore unalterablein
the future.BoththeProtectEnable(PRE)andWrite
Enable (W) input pins must be driven High during
the instruction execution. The OTP bit cannot be
directly read, it can be checked by reading the
content of the Protect Register (PRREAD instruc-
tion), then by writing this same value into the Pro-
tect Register (PRWRITE instruction): when the
OTP bit is set, the Ready/Busy status cannot ap-
pear on the Data output (Q); when the OTPbit is
not set, the Busystatus appearon the Data output
(Q).
APREN instruction must immediately precede the
PRDS instruction.
READY/BUSYStatus
When the ST93CS46/47 is performing the write
cycle, the Busy signal (Q = 0) is returned if S is
driven high, and the ST93CS46/47will ignore any
dataonthebus.Whenthewritecycleis completed,
the Readysignal (Q = 1) will indicate, if S is driven
high, that the ST93CS46/47 is ready to receive a
new instruction.Once theST93CS46/47is Ready,
the Data Output Q is setto ’1’ until a new Start bit
is decodedor the Chip Selectis brought Low.
COMMONI/O OPERATION
The DataOutput (Q)andDataInput(D)signalscan
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memorywiththisconnection,mostly toprevent
a short circuit betweenthe lastentered address bit
(A0) and the first data bit output by Q. The reader
should refer to the SGS-THOMSON application
note”MICROWIREEEPROMCommonI/OOpera-
tion”.
MEMORY WRITE PROTECTION
(cont’d)
10/16
ST93CS46, ST93CS47
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