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參數資料
| 型號： | 935272706518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144 |
| 文件頁數： | 31/61頁 |
| 文件大?。?/td> | 326K |
| 代理商： | 935272706518 |
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2004 May 18
37
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
9.19
Clock output register
Table 53 CLKOUTPUT (1Ah) bit allocation
Table 54 CLKOUTPUT (1Ah) bit description
5
DEOENRGB
enables the output DEO to be set to high-impedance
0 = active signal
1 = high-impedance
4
HSOENRGB
enables the output HSYNCO to be set to high-impedance
0 = active signal
1 = high-impedance
3
HPDOEN
enables the output HPDO to be set to high-impedance
0 = active signal
1 = high-impedance
2
VSOENRGB
enables the output VSYNCO to be set to high-impedance
0 = active signal
1 = high-impedance
1
CLPOEN
enables the output CLPO to be set to high-impedance
0 = active signal
1 = high-impedance
0
FIELDOEN
enables the output FIELDO to be set to high-impedance
0 = active signal
1 = high-impedance
BIT
7
6
5
43210
Symbol
CKSELRGB
DLYCLKRGB
CKDATINV
OUTOSCILL
CKOENRGB
Default
X
00001
BIT
SYMBOL
DESCRIPTION
7 to 5
not used
4
CKSELRGB
enables the selection of the signal on the pin CKDATA
0 = clock of output buffers; signal Ckdata
1 = pixel clock of the converter; signal Ckadco
3
DLYCLKRGB
enables a delay of 2 ns to be added to the clock Ckdata
0 = no delay
1 = 2 ns delay
2
CKDATINV
enables the polarity of the output CKDATA to be inverted
0 = non-inverted
1 = inverted
1
OUTOSCILL
enables pin CKDATA to be switched with a multiplexer to have signal Ckdata or the
internal oscillator on the output
0 = Ckdata
1 = for test
BIT
SYMBOL
DESCRIPTION
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