參數(shù)資料
型號： 935272706518
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144
文件頁數(shù)： 25/61頁
文件大小： 326K
代理商： 935272706518
2004 May 18
31
Philips Semiconductors
Product specication
Triple 8-bit video ADC up to 270 Msps
TDA8754
Table 32 DIVLSB (0Dh) bit allocation
Table 33 DIVLSB (0Dh) bit description
Table 34 PLL divider ratio
9.10
Horizontal sync registers
Remark: The sum of HSYNCL[9:0] + HBACKL[9:0] + HDISPL[9:0] + 16 needs to be smaller than the PLL divider.
Table 35 HSYNCL, HBACKL and HDISPL bits allocation
Table 36 Sync registers (0Eh to 11h) bit description
BIT
76543210
Symbol
DI7
DI6
DI5
DI4
DI3
DI2
DI1
D0
Default
1
0
1
0
BIT
SYMBOL
DESCRIPTION
7 to 0
DI[7:0]
PLL divider ratio. These are the 8 LSBs of the 12-bit value. See Table 34.
DI11 DI10
DI9
DI8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
PLL DIVIDER RATIO
000001100100
100
::::::::::::
:
111111111111
4095
BIT
76543210
Register address 0Eh
Symbol
HSYNCL9
HSYNCL8
HSYNCL7
HSYNCL6
HSYNCL5
HSYNCL4
HSYNCL3
HSYNCL2
Default
0
1
0
1
0
Register address 0Fh
Symbol
HSYNCL1
HSYNCL0
HBACKL9
HBACKL8
HBACKL7
HBACKL6
HBACKL5
HBACKL4
Default
0
1
Register address 10h
Symbol
HBACKL3
HBACKL2
HBACKL1
HBACKL0
HDISPL11
HDISPL10
HDISPL9
HDISPL8
Default
1
0
1
0
1
Register address 11h
Symbol
HDISPL7
HDISPL6
HDISPL5
HDISPL4
HDISPL3
HDISPL2
HDISPL1
HDISPL0
Default
0
BIT
SYMBOL
DESCRIPTION
HSYNCL[9:0]
length of the Hsync signal; in number of pixel clock cycles; minimum value
is 16
HBACKL[9:0]
interval between the Hsync active edge and the rst active pixel; in number of
pixels; minimum value is 16
HDISPL[11:0]
number of active pixels for one line; length of the data enable signal; minimum
value is 16
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