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參數(shù)資料
| 型號： | 935272535118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 封裝： | 4.50 X 7MM, 0.65 MM HEIGHT, PLASTIC, MO-225, SOT-702-1, VFBGA-56 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 102K |
| 代理商： | 935272535118 |
Philips Semiconductors
Product data
SSTV16857
14-bit SSTL_2 registered driver
with differential clock inputs
2002 Sep 27
6
TIMING REQUIREMENTS
Over recommended operating conditions; Tamb = 0 to +70 °C (unless otherwise noted) (see Figure 1)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
VCC = 2.5 V ±0.2 V
UNIT
MIN
MAX
fclock
Clock frequency
—
200
MHz
tw
Pulse duration, CLK, CLK HIGH or LOW
1.0
—
ns
t
Setup time
Data before CLK
↑, CLK↓
0.2
—
ns
tsu
Setup time
RESET HIGH before CLK
↑, CLK↓
0.8
—
ns
th
Hold time
0.75
—
ns
SWITCHING CHARACTERISTICS
Over recommended operating conditions; Tamb = 0 to +70 °C; VDDQ = 2.3 – 2.7 V and VDDQ does not exceed VCC.
Class I, VREF = VTT = VDDQ × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1)
LIMITS
SYMBOL
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V ±0.2 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
fmax
Maximum clock frequency
200
—
MHz
tPLH/tPHL
CLK and CLK
Q
1.0
2.8
ns
tPHL
RESET
Q
2.0
4.0
ns
184/200-pin DDR SDRAM DIMM
The PLL clock distribution device and SSTV registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00686
SDRAM
SSTV16857
PCKV857
SSTV16857
FRONT SIDE
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