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參數(shù)資料
| 型號(hào)： | 935272535118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 封裝： | 4.50 X 7MM, 0.65 MM HEIGHT, PLASTIC, MO-225, SOT-702-1, VFBGA-56 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | 935272535118 |
Philips Semiconductors
Product data
SSTV16857
14-bit SSTL_2 registered driver
with differential clock inputs
2002 Sep 27
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
34
RESET
LVCMOS
asynchronous master reset
(Active LOW)
48, 47, 44, 43,
42, 41, 40, 33,
32, 31, 30, 29,
26, 25
D1 – D14
SSTL_2 data inputs
1, 2, 5, 6, 7, 10,
11, 14, 15, 18,
19, 20, 23, 24
Q1 – Q14
SSTL_2 data outputs
35
VREF
SSTL_2 input reference level
3, 8, 13, 17, 22,
27, 36, 46
GND
Ground (0 V)
28, 37, 45
VCC
Positive supply voltage
4, 9, 12, 16, 21
VDDQ
Output supply voltage
38
39
CLK+
CLK–
Differential clock inputs
FUNCTION TABLE
INPUTS
OUTPUT
RESET
CLK
D
Q
L
X
L
H
↓
↑
H
↓
↑
L
H
L or H
X
Q0
H = High voltage level
L = High voltage level
↓ = High-to-Low transition
↑ = Low-to-High transition
X = Don’t care
LOGIC DIAGRAM
SW00763
REGISTER
RESET
VREF
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
CLK+
CLK–
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
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