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參數(shù)資料
| 型號： | 935271530118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 329K |
| 代理商： | 935271530118 |
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
Product data
Rev. 01 — 14 May 2002
10 of 17
9397 750 09791
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
(1) Output-to-output skew is the highest values of positive and negative edge skew:
tsk(o) =tPLHn(max) tPLHn(min) and tsk(o) =tPHLn(max) tPHLn(min) for n = 1 to 10.
(2) Output pulse skew is the highest value of: tsk(p) = |tPLHn tPHLn| for n = 1 to 10.
(3) Part-to-part skew tsk(pr) represents the positive and negative edge skew between outputs of several devices operating under
identical conditions.
Fig 7.
Calculation of tsk(o), tsk(p), and tsk(pr).
tPLH1
tPHL1
tPLH2
tPHL2
tPLH3
tPHL3
tPLH4
tPHL4
tPLH5
tPHL5
tPLH6
tPHL6
tPLH7
tPHL7
tPLH8
tPHL8
tPLH9
tPHL9
tPLH10
tPHL10
A input
Y1 output
Y2 output
Y3 output
Y4 output
Y5 output
Y6 output
Y7 output
Y8 output
Y9 output
Y10 output
002aaa286
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