參數(shù)資料
型號(hào)： 935271490512
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝： PLASTIC, MS-018, SOT-188-2, LCC-68
文件頁(yè)數(shù)： 30/56頁(yè)
文件大?。?/td> 715K
代理商： 935271490512
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
36 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
10. Dynamic characteristics
Table 27:
AC electrical characteristics
Tamb = 40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specied.
Symbol
Parameter
Conditions
2.5 V
3.3 V
5.0 V
Unit
Min
Max
Min
Max
Min
Max
t1w, t2w
clock pulse duration
10
-
6
-
6
-
ns
t3w
oscillator/clock frequency
-
48
-
80
MHz
t6s
address set-up time
0
-
0
-
0
-
ns
t6h
address hold time
0
-
0
-
0
-
ns
t7d
IOR delay from chip select
10
-
10
-
10
-
ns
t7w
IOR strobe width
25 pF load
77
-
26
-
23
-
ns
t7h
chip select hold time from IOR
0
-
0
-
0
-
ns
t9d
read cycle delay
25 pF load
20
-
20
-
20
-
ns
t12d
delay from IOR to data
25 pF load
-
77
-
26
-
23
ns
t12h
data disable time
25 pF load
-
15
-
15
-
15
ns
t13d
IOW delay from chip select
10
-
10
-
10
-
ns
t13w
IOW strobe width
20
-
20
-
15
-
ns
t13h
chip select hold time from IOW
0
-0
-ns
t15d
write cycle delay
25
-
25
-
20
-
ns
t16s
data set-up time
20
-
20
-
15
-
ns
t16h
data hold time
15
-
5
-
5
-
ns
t17d
delay from IOW to output
25 pF load
-
100
-
33
-
29
ns
t18d
delay to set interrupt from Modem
input
25 pF load
-
100
-
24
-
23
ns
t19d
delay to reset interrupt from IOR
25 pF load
-
100
-
24
-
23
ns
t20d
delay from stop to set interrupt
-
1
-
1
-
1
Rclk
t21d
delay from IOR to reset interrupt
25 pF load
-
100
-
29
-
28
ns
t22d
delay from start to set interrupt
-
100
-
45
-
40
ns
t23d
delay from IOW to transmit start
8
24
8
24
8
24
Rclk
t24d
delay from IOW to reset interrupt
-
100
-
45
-
40
ns
t25d
delay from stop to set RXRDY
-
1-
1Rclk
t26d
delay from IOR to reset RXRDY
-
100
-
45
-
40
ns
t27d
delay from IOW to set TXRDY
-
100
-
45
-
40
ns
t28d
delay from start to reset TXRDY
-
8-
8Rclk
t30s
address set-up time
10
-
10
-
10
-
ns
t30w
chip select strobe width
25 pF load
90
-
26
-
23
-
ns
t30h
address hold time
15
-
15
-
15
-
ns
t30d
read cycle delay
25 pF load
20
-
20
-
20
-
ns
t31d
delay from CS to data
25 pF load
-
90
-
26
-
23
ns
t31h
data disable time
25 pF load
-
15
-
15
-
15
ns
t32s
write strobe set-up time
10
-
10
-
10
-
ns
t32h
write strobe hold time
10
-
10
-
10
-
ns
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