
Philips Semiconductors
Product data
PCA9543
2-channel I2C switch with interrupt logic and reset
2
2002 Feb 19
853-2316 27757
FEATURES
1-of-2 bi-directional translating switches
I2C interface logic; compatible with SMBus standards
2 Active Low Interrupt Inputs
Active Low Interrupt Output
Active Low Reset Input
2 address pins allowing up to 4 devices on the I2C bus
Channel selection via I2C bus, in any combination
Power up with all switch channels deselected
Low Rds
ON switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
No glitch on power-up
Supports hot insertion
Low stand-by current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant Inputs
0 to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Package Offer: SO14, TSSOP14
DESCRIPTION
The PCA9543 is a bi-directional translating switch, controlled by the
I2C bus. The SCL/SDA upstream pair fans out to two downstream
pairs, or channels. Any individual SCx/SDx channels or combination
of channels can be selected, determined by the contents of the
programmable control register. Two interrupt inputs, INT0 to INT3,
one for each of the downstream pairs, are provided. One interrupt
output INT, which acts as an AND of the two interrupt inputs, is
provided.
An active-LOW reset input allows the PCA9543 to recover from a
situation where one of the downstream I2C buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I2C state machine and
causes all the channels to be deselected, as does the internal power
on reset function.
The pass gates of the switches are constructed such that the VDD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9543. This allows the use of different bus
voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts
can communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
PIN CONFIGURATION
1
2
3
4
5
6
78
9
10
11
12
13
14
A0
A1
RESET
INT0
SD0
SC0
VSS
VDD
SDA
SCL
SD1
SC1
INT1
INT
SW00803
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
A0
Address input 0
2
A1
Address input 1
3
RESET
Active LOW reset input
4
INT0
Interrupt input 0
5
SD0
Serial data 0
6
SC0
Serial clock 0
7
VSS
Supply ground
8
INT1
Interrupt input 1
9
SD1
Serial data 1
10
SC1
Serial clock 1
11
INT
Interrupt output
12
SCL
Serial clock line
13
SDA
Serial data line
14
VDD
Supply voltage
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
14-Pin Plastic SO
–40 to +85
°C
PCA9543D
SOT108-1
14-Pin Plastic TSSOP
–40 to +85
°C
PCA9543PW
SOT402-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.