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參數(shù)資料
| 型號： | 935271265551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 108K |
| 代理商： | 935271265551 |
Philips Semiconductors
Product data
SSTV16859
2.5 V 13-bit to 26-bit SSTL_2
registered buffer for stacked DDR DIMM
2002 Feb 19
8
TIMING REQUIREMENTS
Over recommended operating conditions; Tamb = 0 to +70 °C (unless otherwise noted) (see Figure 1)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
VDD = 2.5 V ±0.2 V
UNIT
MIN
MAX
fclock
Clock frequency
—
200
MHz
tw
Pulse duration, CK, CK HIGH or LOW
2.5
—
ns
tact
Differential inputs active time
Notes 1, 2
—
22
ns
tinact
Differential inputs inactive time
Notes 1, 3
—
22
ns
t
Setup time, fast slew rate
(see Notes 4 and 6)
Data before CK
↑ CK↓
0.75
ns
tsu
Setup time, slow slew rate
(see Notes 5 and 6)
Data before CK
↑, CK↓
0.9
ns
t
Hold time, fast slew rate
(see Notes 4 and 6)
Data after CK
↑ CK↓
0.75
ns
th
Hold time, slow slew rate
(see Notes 5 and 6)
Data after CK
↑, CK↓
0.9
ns
tSL
Output slew
1
6
V/ns
NOTES:
1. This parameter is not necessarily production tested.
2. Data inputs must be below a minimum time of tact max, after RESET is taken high.
3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken low.
4. For data signal input slew rate
≥ 1 V/ns.
5. For data signal input slew rate
≥ 0.5 V/ns and < 1 V/ns.
6. CK, CK signals input slew rates are
≥ 1 V/ns.
SWITCHING CHARACTERISTICS
Over recommended operating conditions; Tamb = 0 to +70 °C; VDD = 2.3 – 2.7 V.
Class I, VREF = VTT = VDD × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1)
O
LIMITS
SYMBOL
FROM
(INPUT)
TO
(OUTPUT)
VDD = 2.5 V ±0.2 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
fmax
200
—
MHz
tpd
CK and CK
Q
1.1
2.8
ns
tPHL
RESET
Q
1.1
5
ns
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