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參數(shù)資料
| 型號(hào)： | 935271265551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | 935271265551 |
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Philips Semiconductors
Product data
SSTV16859
2.5 V 13-bit to 26-bit SSTL_2
registered buffer for stacked DDR DIMM
2002 Feb 19
7
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = 0 to +70 °C
UNIT
MIN
TYP
MAX
VIK
II = –18 mA, VDD = 2.3 V
—
–1.2
V
VO
IOH = –100 A, VDD = 2.3 to 2.7 V
VDD – 0.2
—
V
VOH
IOH = –16 mA, VDD = 2.3 V
1.95
—
V
VO
IOL = 100 A, VDD = 2.3 to 2.7 V
—
0.2
V
VOL
IOL = 16 mA, VDD = 2.3 V
—
0.35
V
II
All inputs
VI = VDD or GND, VDD = 2.7 V
—
±5
A
Static standby
RESET = GND
—
0.01
IDD
Static operating
RESET = VDD, VI = VIH(AC) or
VIL(AC)
IO = 0, VDD = 2.7 V
—
45
mA
Dynamic operating –
clock only
RESET = VDD, VI = VIH(AC) or
VIL(AC), CK and CK switching
50% duty cycle.
90
—
A/ clock MHz
IDDD
Dynamic operating –
per each data input
RESET = VDD, VI = VIH(AC) or
VIL(AC), CK and CK switching
50% duty cycle. One data input
switching at half clock frequency,
50% duty cycle.
IO = 0, VDD = 2.7 V
20
—
A/ clock MHz/
data input
rOH
Output high
IOH = –20 mA, VDD = 2.3 to 2.7 V
7
—
20
rOL
Output low
IOL = 20 mA, VDD = 2.3 to 2.7 V
7
—
20
rO()
|rOH – rOL|
each separate bit
IO = 20 mA, Tamb = 25°C, VDD = 2.5 V
—
4
Data inputs
VI = VREF ± 310 mV, VDD = 2.5 V
2.5
2.74
3.5
Ci
CK and CK
VICR = 1.25 V, VI(PP) = 360 mV, VDD = 2.5 V
2.5
3.15
3.5
pF
RESET
VI = VDD or GND, VDD = 2.5 V
—
2.27
—
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