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參數(shù)資料
| 型號(hào)： | 935271210112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24 |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | 935271210112 |
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Philips Semiconductors
Product data
PCA9548
8-channel I2C switch with reset
2002 Feb 19
4
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9548 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
A1 A0
0A2
SW00915
1
R/W
FIXED
HARDWARE SELECTABLE
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9548, which will be stored
in the control register. If multiple bytes are received by the
PCA9548, it will save the last byte received. This register can be
written and read via the I2C bus.
B3
B2
B1
B0
SW00932
B7
B6
B5
B4
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL SELECTION BITS
(READ/WRITE)
65
4
2
1
0
73
Figure 4. Control register
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9548 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I2C bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND
X
0
Channel 0
disabled
X
1
Channel 0
enabled
X
0
X
Channel 1
disabled
X
1
X
Channel 1
enabled
X
0
X
Channel 2
disabled
X
1
X
Channel 2
enabled
X
0
X
Channel 3
disabled
X
1
X
Channel 3
enabled
X
0
X
Channel 4
disabled
X
1
X
Channel 4
enabled
X
0
X
Channel 5
disabled
X
1
X
Channel 5
enabled
X
0
X
Channel 6
disabled
X
1
X
Channel 6
enabled
0
X
Channel 7
disabled
1
X
Channel 7
enabled
NOTE: Several channels can be enabled at the same time.
Ex: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0,
means that channels 7, 5, 4, 1, and 0 are disabled and channels 6,
3, and 2 are enabled.
Care should be taken not to exceed the maximum bus capacitance.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of tWL, the PCA9548 will reset its registers and I2C state
machine and will deselect all channels. The RESET input must be
connected to VDD through a pull-up resistor.
POWER-ON RESET
When power is applied to VDD, an internal Power On Reset holds
the PCA9548 in a reset state until VDD has reached VPOR. At this
point, the reset condition is released and the PCA9548 registers and
I2C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
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