參數(shù)資料
型號(hào): 935271210112
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 編、解碼器及復(fù)用、解復(fù)用
英文描述: 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO24
封裝: 7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24
文件頁(yè)數(shù): 7/14頁(yè)
文件大?。?/td> 112K
代理商: 935271210112
Philips Semiconductors
Product data
PCA9548
8-channel I2C switch with reset
2
2002 Feb 19
853-2318 27757
FEATURES
1-of-8 bi-directional translating switches
I2C interface logic; compatible with SMBus standards
Active Low Reset Input
3 address pins allowing up to 8 devices on the I2C bus
Channel selection via I2C bus, in any combination
Power up with all switch channels deselected
Low Rds
ON switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
No glitch on power-up
Supports hot insertion
Low stand-by current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant Inputs
0 to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Package Offer: SO24, TSSOP24
DESCRIPTION
The PCA9548 is a octal bi-directional translating switch controlled
by the I2C bus. The SCL/SDA upstream pair fans out to eight
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable Control Register.
An active-LOW reset input allows the PCA9548 to recover from a
situation where one of the downstream I2C buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I2C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
The pass gates of the switches are constructed such that the VDD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9548. This allows the use of different bus
voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
PIN CONFIGURATION
A0
A1
RESET
SD
SD2
VDD
SDA
SCL
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
SC0
SD1
SC1
A2
SC7
SD7
SC6
SD6
SW00361
VSS
9
16
10
15
11
14
12
13
SC2
SD3
SC3
SC5
SD5
SC4
SD4
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
A0
Address input 0
2
A1
Address input 1
3
RESET
Active LOW reset input
4
SD0
Serial data output 0
5
SC0
Serial clock output 1
6
SD1
Serial data output 1
7
SC1
Serial clock output 2
8
SD2
Serial data output 2
9
SC2
Serial clock output 3
10
SD3
Serial data output 3
11
SC3
Serial clock output 4
12
VSS
Supply ground
13
SD4
Serial data output 4
14
SC4
Serial clock output 5
15
SD5
Serial data output 5
16
SC5
Serial clock output 6
17
SD6
Serial data output 6
18
SC6
Serial clock output 7
19
SD7
Serial data output 7
20
SC7
Serial clock output 8
21
A2
Address input 2
22
SCL
Serial clock line
23
SDA
Serial data line
24
VDD
Supply voltage
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
24-Pin Plastic SO
–40 to +85
°C
PCA9548D
SOT137-1
24-Pin Plastic TSSOP
–40 to +85
°C
PCA9548PW
SOT355-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
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