參數(shù)資料
型號(hào)： 935270497112
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線收發(fā)器
英文描述： GTLP SERIES, 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝： 7.50MM, PLASTIC, MO-118, SOT-371-1, SSOP-56
文件頁(yè)數(shù)： 7/14頁(yè)
文件大小： 147K
代理商： 935270497112
Philips Semiconductors
Product data
GTLPH16612
18-bit GTLP to LVTTL/TTL bidirectional
universal translator (3-State)
2
2001 Sep 28
853–2285 27174
FEATURES
18-bit bidirectional bus interface
Translates between GTLP logic levels (B ports) and LVTTL/TTL
logic levels (A ports)
Edge rate control circuitry on the Bn outputs rising/falling edges to
minimize system noise in a multipoint backplane environment
5 V I/O tolerant on the LVTTL side
No bus current loading when LVTTL output is tied to 5 V bus
3-State buffers
Output capability: +64 mA/-32 mA on the LVTTL side; +40 mA on
the GTLP side
LVTTL input levels on control pins
Power-up reset
Power-up 3-State
Positive edge triggered clock inputs
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 750 V (Bn I/O exceeds 1000 V)
CDM per JESD22-C101
DESCRIPTION
The GTLPH16612 is a high-performance BiCMOS product designed
for VCC operation at 3.3V with I/O compatibility up to 5 V.
The GTLPH16612 is unique in that pin 50 is a no connect and this
device can be used as a replacement device in sockets where
pin 50 is 3.3/5 V VCC or 3.3 V BIAS VCC.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
SYMBOL
PARAMETER
Tamb = 25 °C
3.3 V
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50 pF
1.9
ns
CIN
Input capacitance (Control pins)
VI = 0 V or VCC
4
pF
CI/O
An I/O pin capacitance
VI/O = 0 V or VCC
9
pF
CI/O
Bn I/O pin capacitance
VI/O = 0 V or 1.5 V
5.3
pF
ICCZ
Total supply current
Outputs disabled
12
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DWG NUMBER
56-Pin Plastic SSOP
–40 to +85
°C
GTLPH16612DL
SOT371-1
56-Pin Plastic TSSOP
–40 to +85
°C
GTLPH16612DGG
SOT364-1
NOTE:
1. Standard packing quantities and other packaging data is available at www.philipslogic.com/support/packages.
相關(guān)PDF資料
PDF描述
935270497118 GTLP SERIES, 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
935270496112 GTLP SERIES, 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
935270496118 GTLP SERIES, 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
935270498118 DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8
935270499112 DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8
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