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參數(shù)資料
| 型號： | 935270497112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | GTLP SERIES, 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 7.50MM, PLASTIC, MO-118, SOT-371-1, SSOP-56 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 147K |
| 代理商： | 935270497112 |
Philips Semiconductors
Product data
GTLPH16612
18-bit GTLP to LVTTL/TTL bidirectional universal
translator (3-State)
2001 Sep 28
8
AC SETUP REQUIREMENTS (3.3 V
±0.3 V RANGE)
A Port:
GND = 0 V; Input tr = tf = 2.5 ns; CL = 50 pF; RL = 500 ; Tamb = –40 to +85 °C; VREF = 0.8 V or 1.0 V.
B Port:
GND = 0 V; Input tr = tf = 2.5 ns; CL = 30 pF; RL = 25 ; VREF = 0.8 V or 1.0 V.
LIMITS
SYMBOL
DESCRIPTION
PARAMETER
WAVEFORM
VCC = 3.3 V ±0.3 V
UNIT
MIN
TYP
MAX
tw(H)
Pulse duration
LEAB or LEBA
3
1.0
—
ns
tw(H or L)
Pulse duration
CPAB or CPBA
4
2.5
—
ns
ts(H or L)
Setup time
An before CPAB rising edge
4
2.0
—
ns
ts(H)
Setup time
Bn before CPBA rising edge
4
2.5
—
ns
ts(L)
Setup time
Bn before CPBA rising edge
4
3.1
—
ns
ts(H or L)
Setup time
An before LEAB falling edge
4
0.5
—
ns
ts(H or L)
Setup time
Bn before LEBA falling edge
4
2.5
—
ns
ts(L)
Setup time
CEAB before CPAB rising edge
4
0
—
ns
ts(L)
Setup time
CEBA before CPBA rising edge
4
0
—
ns
th(H or L)
Hold time
An after CPAB rising edge
4
0
—
ns
th(H or L)
Hold time
Bn after CPBA rising edge
4
0
—
ns
th(H or L)
Hold time
An after LEAB falling edge
4
0.5
—
ns
th(H or L)
Hold time
Bn after LEBA falling edge
4
0
—
ns
th(H)
Hold time
CEAB after CPAB rising edge
4
1.1
—
ns
th(H)
Hold time
CEBA after CPBA rising edge
4
1.1
—
ns
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