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參數(shù)資料
| 型號： | 935270390557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, LFBGA-96 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 79K |
| 代理商： | 935270390557 |
2002 Mar 20
8
Philips Semiconductors
Product specication
3.3 V 32-bit edge-triggered D-type ip-op;
3-state
74LVT32374
AC CHARACTERISTICS
GND = 0 V; tr =tf ≤ 2.5 ns; CL = 50 pF; RL = 500 .
Note
1. All typical values are measured at VCC = 3.3 V and Tamb =25 °C.
AC SETUP REQUIREMENTS
GND = 0 V; tr =tf = 2.5 ns; CL = 50 pF; RL = 500 ; Tamb = 40 to +125 °C.
SYMBOL
PARAMETER
WAVEFORMS
VCC = 3.3 ±0.3 V
VCC = 2.7 V
UNIT
MIN.
TYP.(1)
MAX.
tPLH/tPHL
propagation delay
nCP to nQn
see Fig.5
1.5
3.0
5.3
6.2
ns
1.5
3.0
4.9
5.1
ns
tPZH/tPZL
output enable time to
HIGH and LOW level
see Figs 7 and 8
1.5
3.5
5.6
6.9
ns
1.5
3.2
4.9
6.0
ns
tPHZ/tPLZ
output disable time from
HIGH and LOW level
see Figs 7 and 8
1.5
3.5
5.4
5.7
ns
1.5
3.2
5.0
5.1
ns
fmax
maximum clock pulse
frequency
see Fig.5
150
MHz
SYMBOL
PARAMETER
WAVEFORMS
VCC = 3.3 ±0.3 V
VCC = 2.7 V
UNIT
MIN.
TYP.(1)
MIN.
tsuH
set-up time nDn HIGH to nCP
see Fig.6
2.5
0.7
2.5
ns
tsuL
set-up time nDn LOW to nCP
see Fig.6
2.5
0.7
2.5
ns
thH
hold time nDn HIGH to nCP
see Fig.6
0.5
0
ns
thL
hold time nDn LOW to nCP
see Fig.6
0.5
0
ns
tWH
nCP HIGH pulse width
see Fig.6
1.5
0.6
1.5
ns
tWL
nCP LOW pulse width
see Fig.6
3.0
1.6
3.0
ns
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