參數(shù)資料
型號(hào)： 935270075551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁(yè)數(shù)： 7/56頁(yè)
文件大小： 715K
代理商： 935270075551
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
15 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.4 Internal registers
The SC16C554/554D provides 15 internal registers for monitoring and control. These
registers are shown in Table 5. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C554
features and capabilities, the SC16C554/554D offers an enhanced feature register
set (EFR, Xon/Xoff1-2) that provides on-board hardware/software ow control.
Register functions are more fully described in the following paragraphs.
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
[3]
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF’ (HEX).
6.5 FIFO operation
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. With SC16C554 devices, the user can set the receive trigger
level, but not the transmit trigger level. The receiver FIFO section includes a time-out
function to ensure data is delivered to the external CPU. An interrupt is generated
whenever the Receive Holding Register (RHR) has not been read following the
loading of a character or the receive trigger level has not been reached. (For a
description of this timing, see Section 6.6 “Hardware ow control”.)
Table 5:
Internal registers decoding
A2
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)[3]
0
1
0
Enhanced Feature Register
1
0
Xon1 word
1
0
1
Xon2 word
1
0
Xoff1 word
1
Xoff2 word
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