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| 型號： | 935270075551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 26/56頁 |
| 文件大小： | 715K |
| 代理商： | 935270075551 |
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Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
32 of 53
9397 750 11002
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C554/554D provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software ow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
1
MSR[1]
DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic1=The DSR input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
Table 20:
Modem Status Register bits description…continued
Bit
Symbol
Description
Table 21:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Auto CTS. Automatic CTS Flow Control.
Logic 0 = Automatic CTS ow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS ow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Auto RTS. Automatic RTS may be used for hardware ow control by
enabling EFR[6]. When Auto RTS is selected, an interrupt will be
generated when the receive FIFO is lled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return
to a logic 0 when data is unloaded below the next lower trigger level
(Programmed trigger level -1). The state of this register bit changes with
the status of the hardware ow control. RTS functions normally when
hardware ow control is disabled.
Logic 0 = Automatic RTS ow control is disabled (normal default
condition).
Logic 1 = Enable Automatic RTS ow control.
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