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| 型號： | 935270054157 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 2/48頁 |
| 文件大?。?/td> | 657K |
| 代理商： | 935270054157 |
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Philips Semiconductors
SC16C750
Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
Product data
Rev. 03 — 14 March 2003
10 of 45
9397 750 11203
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
[3]
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF(HEX)’.
6.2 FIFO operation
The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The SC16C750 provides independent trigger
levels for both receiver and transmitter. To remain compatible with SC16C550, the
transmit interrupt trigger level is set to 16 following a reset. It should be noted that the
user can set the transmit trigger levels by writing to the FCR register, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes
a time-out function to ensure data is delivered to the external CPU. An interrupt is
generated whenever the Receive Holding Register (RHR) has not been read
following the loading of a character or the receive trigger level has not been reached.
Table 3:
Internal registers decoding
A2
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)[3]
0
1
0
Enhanced Feature Register
1
0
Xon1 word
1
0
1
Xon2 word
1
0
Xoff1 word
1
Xoff2 word
Table 4:
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS
Assert RTS
16-byte FIFO
11
4
1
44
8
4
8
12
8
14
10
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