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參數(shù)資料
| 型號： | 935270053529 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-018, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大?。?/td> | 657K |
| 代理商： | 935270053529 |
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Philips Semiconductors
SC16C750
Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
Product data
Rev. 03 — 14 March 2003
14 of 45
9397 750 11203
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.7 Sleep mode
The SC16C750 is designed to operate with low power consumption. A special sleep
mode is included to further reduce power consumption when the chip is not being
used. With IER[4] enabled (set to a logic 1), the SC16C750 enters the sleep mode,
but resumes normal operation when a start bit is detected, a change of state on any
of the modem input pins RX, RI, CTS, DSR, DCD, or a transmit data is provided by
the user. If the sleep mode is enabled and the SC16C750 is awakened by one of the
conditions described above, it will return to the sleep mode automatically after the last
character is transmitted or read by the user. In any case, the sleep mode will not be
entered while an interrupt(s) is pending. The SC16C750 will stay in the sleep mode of
operation until it is disabled by setting IER[4] to a logic 0.
6.8 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and recongured for loop-back
internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 2-3) control the
modem RI and DCD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
used to control the modem CTS and DSR inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see Figure 5). The CTS, DSR,
DCD, and RI are disconnected from their normal modem control input pins, and
instead are connected internally to DTR, RTS, OUT1 and OUT2. Loop-back test data
is entered into the transmit holding register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the serial data to the receive
UART via the internal loop-back connection. The receive UART converts the serial
data back into parallel data that is then made available at the user data interface
D0-D7. The user optionally compares the received data to the initial transmitted data
for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0-3]) instead of the four
Modem Status Register bits 4-7. The interrupts are still controlled by the IER.
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