- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24832 > 935270053529 (NXP SEMICONDUCTORS) 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44 PDF資料下載
參數(shù)資料
| 型號： | 935270053529 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-018, SOT-187-2, LCC-44 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 657K |
| 代理商： | 935270053529 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Philips Semiconductors
SC16C750
Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
Product data
Rev. 03 — 14 March 2003
21 of 45
9397 750 11203
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.4 Interrupt Status Register (ISR)
The SC16C750 provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits. Table 12 “Interrupt source” shows the data values
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12:
Interrupt source
Priority
level
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0110
LSR (Receiver Line Status Register)
2
0100
RXRDY (Received Data Ready)
2
1100
RXRDY (Receive Data time-out)
3
0010
TXRDY (Transmitter Holding Register
Empty)
4
0000
MSR (Modem Status Register)
Table 13:
Interrupt Status Register bits description
Bit
Symbol
Description
7-6
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared = default condition.
5
ISR[5]
64-byte FIFO enable.
Logic 0 = 16-byte operation.
Logic 1 = 64-byte operation.
4
ISR[4]
Not used.
3-1
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).
Logic 0 or cleared = default condition.
0
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935270053512 | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 935270053518 | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 935270054157 | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 08051C103JA74A | General Specifications |
| 935270056529 | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
| 935270792551 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270792557 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270793551 | 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA |
| 935270793557 | 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。