參數(shù)資料
型號: 935270051512
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝: PLASTIC, MS-018, SOT-188-2, LCC-68
文件頁數(shù): 49/55頁
文件大小: 706K
代理商: 935270051512
Philips Semiconductors - PIP - SC16C654/654D; Quad UART with 64-byte FIFO and infrared (IrDA)encoder/decoder
Product Information
SC16C654/654D; Quad
UART with 64-byte
FIFO and infrared
(IrDA)encoder/decoder
Information as of 2003-04-22
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Parametrics
topGeneral description
The SC16C654/654D is a 4-channel Universal Asynchronous Receiver and Transmitter (QUART) used for serial
data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART
can handle serial data rates up to 5 Mbits/s. It comes with an Intel or Motorola interface.
The SC16C654/654D is pin compatible with the ST16C654 and TL16C754 and it will power-up to be functionally
equivalent to the 16C454. Programming of control registers enables the added features of the SC16C654/654D.
Some of these added features are the 64-byte receive and transmit FIFOs, automatic hardware or software flow
control and Infrared encoding/decoding. The selectable auto-flow control feature significantly reduces software
overload and increases system efficiency while in FIFO mode by automatically controlling serial data flow using
RTS output and CTS input signals. The SC16C654/654D also provides DMA mode data transfers through FIFO
trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error
indications, operational status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The SC16C654/654D operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature range, and is available in
plastic PLCC68 and LQFP64 packages.
topFeatures
q
5 V, 3.3 V and 2.5 V operation
q
Industrial temperature range
q
Pin compatibility with the industry-standard ST16C454/554, ST68C454/554, TL16C554
q
Up to 5 Mbits/s data rate at 5 V and 3.3 V and 3 Mbits/s at 2.5 V
q
64-byte transmit FIFO
q
64-byte receive FIFO with error flags
q
Automatic software/hardware flow control
q
Programmable Xon/Xoff characters
q
Software selectable Baud Rate Generator
q
Four selectable Receive and Transmit FIFO interrupt trigger levels
q
Standard modem interface or infrared IrDA encoder/decoder interface
q
Sleep mode
q
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
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