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參數資料
| 型號： | 935269807118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, MO-118, SOT-370-1, SSOP-48 |
| 文件頁數： | 7/12頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 935269807118 |
Philips Semiconductors
Product data
PCK2002
0–300 MHz I2C 1:18 clock buffer
2001 Jun 19
4
DC CHARACTERISTICS
TEST CONDITIONS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = 0 to +70 °C
UNIT
VDD (V)
OTHER
MIN
MAX
VIH
HIGH level input voltage
3.135 to 3.465
2.0
VDD + 0.3
V
VIL
LOW level input voltage
3.135 to 3.465
VSS – 0.3
0.8
V
VO
3 3V output HIGH voltage
3.135 to 3.465
IOH = –1 mA
VCC – 0.1
—
V
VOH
3.3V output HIGH voltage
3.135
IOH = –36 mA
2.4
—
V
VO
3 3V output LOW voltage
3.135 to 3.465
IOL= 1 mA
—
0.1
V
VOL
3.3V output LOW voltage
3.135
IOL= 24 mA
—
0.4
V
IO
Output HIGH current
3.135
VOUT = 2.0 V
–54
–126
mA
IOH
Output HIGH current
3.465
VOUT = 3.135 V
–21
–46
mA
IO
Output LOW current
3.135 to 3.465
VOUT = 1.0 V
49
118
mA
IOL
Output LOW current
3.135 to 3.465
VOUT = 0.4 V
24
53
mA
±II
Input leakage current
3.465
—
±5
A
±IOZ
3-State output OFF-State current
3.465
VOUT = VDDor GND
IO = 0
—
10
A
ICC
Quiescent supply current
3.465
VI = VDD or GND
IO = 0
—
100
A
ICC
Additional quiescent supply
current given per control pin
3.135 to 3.465
VI = VDD– 0.6V
IO = 0
—
500
A
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Tamb = 0 to +70 °C
UNIT
NOTES
MIN
TYP6
MAX
TSDRISE
SDRAM rise time
2, 4
1.5
2.0
4.0
V/ns
TSDFALL
SDRAM fall time
2, 4
1.5
2.9
4.0
V/ns
TPLH
SDRAM buffer LH propagation delay
4, 5
1.2
2.7
3.5
ns
TPHL
SDRAM buffer HL propagation delay
4, 5
1.2
2.9
3.5
ns
TPZL, TPZH
SDRAM buffer enable time
4, 5
1.0
2.6
5.0
ns
TPLZ, TPHZ
SDRAM buffer disable time
4, 5
1.0
2.7
5.0
ns
DUTY CYCLE
Output Duty Cycle
Measured at 1.5 V
3, 4, 5
45
52
55
%
TSDSKW
SDRAM Bus CLK skew
1, 4
—
150
250
ps
TDDSKW
Device to device skew
—
500
ps
NOTES:
1. Skew is measured on the rising edge at 1.5 V.
2. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1mA) JEDEC specification.
3. Duty cycle should be tested with a 50/50% input.
4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.
5. Input edge rate for these tests must be faster than 1 V/ns.
6. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
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