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參數(shù)資料
| 型號(hào)： | 935268282151 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935268282151 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
13
12.0
OTHER DEVICE I/O
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
See Note 1
—
81
—
mA
IDD
Supply current
See Note 2
—
56
—
mA
See Note 3
—
50
—
mA
IDD–PD
Supply current in power down mode
PD = VDD in power down mode
—
150
—
A
VTH
Cable power status threshold voltage
390 k
resistor between cable power
and CPS pin: Measured at cable power
side of resistor
4.7
—
7.5
V
Hi h l
l
t
lt
i
CTL0
VDD = 2.7 V, IOH = –4 mA, ISO = VDD
2.4
—
V
VOH
High-level output voltage, pins CTL0,
CTL1, D0–D7, SYSCLK, CNA
VDD >= 3.0 V, IOH = –4 mA, ISO = VDD
2.8
—
V
CTL1, D0 D7, SYSCLK, CNA
Annex J: IOH = –9 mA, ISO = 0
VDD–0.4
—
V
VO
Low-level output voltage, pins CTL0,
IOL = 4 mA, ISO = VDD
—
0.4
V
VOL
g,
,
CTL1, D0–D7, CNA, SYSCLK
Annex J: IOL = 9 mA, ISO = 0
—
0.4
V
VO
High level output voltage pin C/LKON
VDD = 2.7 V, IOH = –4 mA; See Note 4
2.4
—
V
VOH
High-level output voltage, pin C/LKON
VDD >= 3.0 V, IOH = –4 mA; See Note 4
2.7
—
V
VOL
Low-level output voltage, pin C/LKON
VDD = 2.7 V, IOL = 4 mA; See Note 4
—
0.3
V
IBH+
Positive peak bus holder current, pins
CTL0, CTL1, D0–D7, LREQ
ISO = VDD, VI = 0 V to VDD
0.05
—
1.0
mA
IBH–
Negative peak bus holder current, pins
CTL0, CTL1, D0–D7, LREQ
ISO = VDD, VI = 0 V to VDD
–1.0
—
–0.05
mA
II
Input current, pins LREQ, LPS, PD,
TEST0, BRIDGE, PC0–PC2
ISO = 0 V; VDD = 3.6 V
—
5
A
IOZ
Off-state current, pins CTL0, CTL1,
D0–D7, C/LKON
VO = VDD or 0 V
–5
—
5
A
IRST-UP
Pullup current, RESET input
VI = 1.5 V or 0 V
–90
—
–20
A
IRST-DN
Pulldown current, RESET input
VI = VDD, PD = VDD
.4
1.6
2.8
mA
VIT+
Positive going threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
ISO = 0 V
VDD/2 + 0.3
—
VDD/2 + 0.9
V
VIT–
Negative going threshold voltage, LREQ,
CTL0, CTL1, D0–D7 inputs
ISO = 0 V
VDD/2 – 0.9
—
VDD/2 – 0.3
V
VLIT+
Positive going threshold voltage, LPS
inputs
VLREF = 0.42 x VDD
—
VLREF+1
V
VLIT–
Negative going threshold voltage, LPS
inputs
VLREF = 0.42 x VDD
VLREF+0.2
—
V
VO
TPBIAS output voltage
At rated IO current
1.665
—
2.015
V
NOTES:
1. Transmit Max Packet (2 ports transmitting max size isochronous packet (4096 bytes), sent on every isochronous interval, S400, data value
of 0xCCCCCCCCh), VDD = 3.3 V, TA = 25 °C
2. Repeat typical packet (1 port receiving DV packets on every isochronous interval, 1 port repeating the packet, S100), VDD = 3.3 V,
TA = 25
°C
3. Idle (receive cycle start on one port, transmit cycle start on other port) VDD = 3.3 V, TA = 25 °C
4. The C/LKON pin is able to drive an isolation circuit according to Figure 5A-20 of the IEEE-1394a-2000 standard.
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