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參數(shù)資料
| 型號： | 935268282151 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 3/42頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935268282151 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
11
9.0
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
VDD
Supply voltage
Source power node
3.0
3.3
3.6
V
VDD
Su
ly voltage
Non-source power node
2.7 1
3.0
3.6
V
High-level input voltage, LREQ,
ISO = VDD, VDD >= 2.7 V
2.3
—
V
gg
CTL0, CTL1, D0-D7
ISO = VDD, VDD >= 3.0 V
2.6
—
V
VIH
High-level input voltage, C/LKON2,
PC0–PC2, ISO, PD
0.7 VDD
—
V
High-level input voltage, RESET
0.6 VDD
—
Low-level input voltage, LREQ,
CTL0, CTL1, D0–D7
ISO = VDD
—
0.7
V
VIL
Low-level input voltage, C/LKON2,
PC0–PC2, ISO, PD,
—
0.2 VDD
V
Low-level input voltage, RESET
—
0.3 VDD
—
IO
Output current
TPBIAS outputs
–6
2.5
mA
VID
Differential input voltage amplitude
TPA, TPB cable inputs, during data reception
118
—
260
mV
VID
Differential in ut voltage am litude
TPA, TPB cable inputs, during data arbitration
168
—
265
mV
VIC 100
TPB common-mode input voltage
Speed signaling off
Source power node
1.165
—
2.515
V
VIC-100
TPB common-mode in ut voltage
gg
or S100 speed signal
Non-source power node
1.165
—
2.0151
V
VIC 200
TPB common-mode input voltage
S200 speed signal
Source power node
0.935
—
2.515
V
VIC-200
TPB common-mode in ut voltage
S200 s eed signal
Non-source power node
0.935
—
2.0151
V
VIC 400
TPB common-mode input voltage
S400 speed signal
Source power node
0.523
—
2.515
V
VIC-400
TPB common-mode in ut voltage
S400 s eed signal
Non-source power node
0.523
—
2.0151
V
tPU
Power-up reset time
Set by capacitor between RESET pin and GND
2
—
ms
TPA, TPB cable inputs, S100 operation
—
1.08
ns
Receive input jitter
TPA, TPB cable inputs, S200 operation
—
0.5
ns
TPA, TPB cable inputs, S400 operation
—
0.315
ns
Between TPA and TPB cable inputs, S100 operation
—
0.8
ns
Receive input skew
Between TPA and TPB cable inputs, S200 operation
—
0.55
ns
Between TPA and TPB cable inputs, S400 operation
—
0.5
ns
fXTAL
Crystal or external clock frequency
Crystal connected according to Figure 10 or external
clock input at pin XI
24.5735
24.576
24.5785
MHz
NOTES:
1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).
2. C/LKON is only an input when RESET = 0.
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