參數(shù)資料
型號(hào)： 935268252551
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁數(shù)： 6/80頁
文件大小： 306K
代理商： 935268252551
Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
11
DEFAULT BUFFER SIZE
BUFFER MEMORY
SIZE
(Quadlets)
Asynchronous Receive Response FIFO
256
Asynchronous Receive Request FIFO
256
Asynchronous Transmit Response FIFO
256
Asynchronous Transmit Request FIFO
256
Isochronous (AV) Transmit Buffer
1024
Isochronous (AV) Receive Buffer
1024
12.3
Bushold and Link/PHY single capacitor galvanic isolation
12.3.1
Bushold
The PDI1394L40 uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by
a 3-Stated device or input coupling capacitor. Unterminated high impedance inputs react to ambient electrical noise which cause internal
oscillation and excess power supply current draw.
The following pins have bushold circuitry enabled when the ISON pin is in the logic “1” state:
Name
Function
PHY CTL0
PHY control line 0
PHY CTL1
PHY control line 1
PHY D0
PHY data bus bit 0
PHY D1
PHY data bus bit 1
PHY D2
PHY data bus bit 2
PHY D3
PHY data bus bit 3
PHY D4
PHY data bus bit 4
PHY D5
PHY data bus bit 5
PHY D6
PHY data bus bit 6
PHY D7
PHY data bus bit 7
SYSCLK
System clock input to the link
Philips bushold circuitry is designed to provide a high resistance pull-up or pull-down on the input pin. This high resistance is easily overcome
by the driving device when its state is switched. Figure 2 shows a typical bushold circuit applied to a CMOS input stage. Two weak MOS
transistors are connected to the input. An inverter is also connected to the input pin and supplies gate drive to both transistors. When the input
is LOW, the inverter output drives the lower MOS transistor and turns it on. This re-enforces the LOW on the input pin. If the logic device which
normally drives the input pin were to be 3-Stated, the input pin would remain “pulled-down” by the weak MOS transistor. If the driving logic
device drives the input pin HIGH, the inverter will turn the upper MOS transistor on, re-enforcing the HIGH on the input pin. If the driving logic
device is then 3-Stated, the upper MOS transistor will weakly hold the input pin HIGH.
The PHY’s outputs can be 3-Stated and single capacitor isolation can be used with the Link; both situations will allow the Link inputs to float.
With bushold circuitry enabled, these pins are provided with dc paths to ground, and power by means of the bushold transistors; this
arrangement keeps the inputs in known logical states.
SV00911
INPUT PIN
INTERNAL
CIRCUITS
Figure 2.
Bushold circuit
相關(guān)PDF資料
PDF描述
08008GOC 125 A, 800 V, SCR, TO-209AC
08008GOD 125 A, 800 V, SCR, TO-208AD
08010GOB 125 A, 1000 V, SCR, TO-209AC
08010GOC 125 A, 1000 V, SCR, TO-209AC
08010GOD 125 A, 1000 V, SCR, TO-208AD
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