參數(shù)資料
型號： 935263652557
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, SOT-393, QFP-64
文件頁數(shù)： 26/75頁
文件大?。?/td> 479K
代理商： 935263652557
1998 May 15
32
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
Fig.24 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0.
(2) Additional VREF positions can be achieved via I2C-bits VCTR1 and VCTR0 (see Fig.9).
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
handbook, full pagewidth
313
314
315
316
317
318
319
335
336
12
3
4
5
6
78
22
625
HREF
input CVBS
(b) 2nd field
(a) 1st field
VREF
VRLN = 1(2)
VRLN = 0(2)
624
623
622
23
HREF
input CVBS
312
311
310
VRLN = 0(2)
337
MGG069
535 x 2/LLC
VS
RTS0 (ODD)(1)
320
VS
77 x 2/LLC
VRLN = 1(2)
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