參數(shù)資料
型號(hào)： 935263652557
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, SOT-393, QFP-64
文件頁數(shù)： 17/75頁
文件大?。?/td> 479K
代理商： 935263652557
1998 May 15
24
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
αcs
channel crosstalk
fi = 5 MHz
50
dB
Analog-to-digital converters
B
bandwidth
at
3dB
7
MHz
φ
diff
differential phase
(amplier plus anti-alias
lter = bypass)
2
deg
Gdiff
differential gain
(amplier plus anti-alias
lter = bypass)
2
%
fclkADC
ADC clock frequency
12.8
14.3
MHz
DLE
DC differential linearity
error
0.7
LSB
ILE
DC integral linearity error
1
LSB
Digital inputs
VIL(SCL,SDA)
LOW level input voltage
pins SDA and SCL
0.5
+0.3VDDD
V
VIH
HIGH level input voltage
pins SDA and SCL
0.7VDDD
VDDD + 0.5
V
VIL(xtal)
LOW level CMOS input
voltage pin XTALI
0.3
+0.8
V
VIH(xtal)
HIGH level CMOS input
voltage pin XTALI
2.0
VDDD + 0.3
V
VILn
LOW level input voltage all
other inputs
0.3
+0.8
V
VIHn
HIGH level input voltage
all other inputs
2.0
5.5
V
ILI
input leakage current
1
A
Ci
input capacitance
outputs at 3-state
8pF
Ci(n)
input capacitance all other
inputs
5pF
Digital outputs
VOL(SCL,SDA)
LOW level output voltage
pins SDA and SCL
SDA/SCL at 3 mA (6 mA)
sink current
0.4 (0.6)
V
VOL
LOW level output voltage
VDDD = max; IOL =2mA
0
0.4
V
VOH
HIGH level output voltage
VDDD = min, IOH = 2 mA
2.4
VDDD + 0.5
V
VOL(clk)
LOW level output voltage
for clocks
0.5
+0.6
V
VOH(clk)
HIGH level output voltage
for clocks
2.4
VDDD + 0.5
V
ILO
output leakage current
at 3-state mode
10
A
FEI input timing
tSU;DAT
input data set-up time
13
ns
tHD;DAT
input data hold time
3
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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